Commit 51a4c38a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'mediatek-drm-fixes-2016-11-11' of... 

Merge branch 'mediatek-drm-fixes-2016-11-11' of https://github.com/ckhu-mediatek/linux.git-tags into drm-fixes

This branch include one patch to fix a typo, two patches to disable
vblank interrupt, and three patches to support HDMI 4K resolution.

* 'mediatek-drm-fixes-2016-11-11' of https://github.com/ckhu-mediatek/linux.git-tags:
  drm/mediatek: modify the factor to make the pll_rate set in the 1G-2G range
  drm/mediatek: enhance the HDMI driving current
  drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable
  drm/mediatek: clear IRQ status before enable OVL interrupt
  drm/mediatek: set vblank_disable_allowed to true
  drm/mediatek: fix a typo of OD_CFG to OD_RELAYMODE
parents 94ea29b1 0d220079

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

+1 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp, 
						 ddp_comp);



	priv->crtc = crtc;

	writel(0x0, comp->regs + DISP_REG_OVL_INTSTA);

	writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN);

}

drivers/gpu/drm/mediatek/mtk_dpi.c

+7 −2
Original line number Diff line number Diff line
@@ -432,11 +432,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, 
	unsigned long pll_rate;

	unsigned int factor;



	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */

	pix_rate = 1000UL * mode->clock;

	if (mode->clock <= 74000)

	if (mode->clock <= 27000)

		factor = 16 * 3;

	else if (mode->clock <= 84000)

		factor = 8 * 3;

	else

	else if (mode->clock <= 167000)

		factor = 4 * 3;

	else

		factor = 2 * 3;

	pll_rate = pix_rate * factor;



	dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",

drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c

+1 −1
Original line number Diff line number Diff line
@@ -123,7 +123,7 @@ static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w, 
			  unsigned int bpc)

{

	writel(w << 16 | h, comp->regs + DISP_OD_SIZE);

	writel(OD_RELAYMODE, comp->regs + OD_RELAYMODE);

	writel(OD_RELAYMODE, comp->regs + OD_CFG);

	mtk_dither_set(comp, bpc, DISP_OD_CFG);

}

drivers/gpu/drm/mediatek/mtk_drm_drv.c

+1 −0
Original line number Diff line number Diff line
@@ -217,6 +217,7 @@ static int mtk_drm_kms_init(struct drm_device *drm) 
	if (ret < 0)

		goto err_component_unbind;



	drm->vblank_disable_allowed = true;

	drm_kms_helper_poll_init(drm);

	drm_mode_config_reset(drm);

drivers/gpu/drm/mediatek/mtk_hdmi.c

+11 −6
Original line number Diff line number Diff line
@@ -1133,12 +1133,6 @@ static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi, 
	phy_power_on(hdmi->phy);

	mtk_hdmi_aud_output_config(hdmi, mode);



	mtk_hdmi_setup_audio_infoframe(hdmi);

	mtk_hdmi_setup_avi_infoframe(hdmi, mode);

	mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");

	if (mode->flags & DRM_MODE_FLAG_3D_MASK)

		mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);



	mtk_hdmi_hw_vid_black(hdmi, false);

	mtk_hdmi_hw_aud_unmute(hdmi);

	mtk_hdmi_hw_send_av_unmute(hdmi);
@@ -1401,6 +1395,16 @@ static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge) 
	hdmi->powered = true;

}



static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,

				    struct drm_display_mode *mode)

{

	mtk_hdmi_setup_audio_infoframe(hdmi);

	mtk_hdmi_setup_avi_infoframe(hdmi, mode);

	mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");

	if (mode->flags & DRM_MODE_FLAG_3D_MASK)

		mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);

}



static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)

{

	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
@@ -1409,6 +1413,7 @@ static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge) 
	clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);

	clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);

	phy_power_on(hdmi->phy);

	mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);



	hdmi->enabled = true;

}

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