Commit 0d220079 authored Sep 29, 2016 by Junzhi Zhao Committed by CK Hu Oct 19, 2016

drm/mediatek: modify the factor to make the pll_rate set in the 1G-2G range



Currently, the code sets the "pll" to the desired multiple
of the pixel clock manully(4*3m 8*3,etc).  The valid range
of the pll is 1G-2G, however, when the pixel clock is bigger
than 167MHz,  the "pll" will be set to a invalid value( > 2G),
then the "pll" will be 2GHz, thus the pixel clock will be in
correct. Change the factor to make the "pll" be set in the
(1G, 2G) range.

Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com>
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>

parent 968253bd

drivers/gpu/drm/mediatek/mtk_dpi.c

+7 −2

Original line number	Diff line number	Diff line
		@@ -432,11 +432,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
		unsigned long pll_rate;
		unsigned int factor;

		/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
		pix_rate = 1000UL * mode->clock;
		if (mode->clock <= 74000)
		if (mode->clock <= 27000)
		factor = 16 * 3;
		else if (mode->clock <= 84000)
		factor = 8 * 3;
		else
		else if (mode->clock <= 167000)
		factor = 4 * 3;
		else
		factor = 2 * 3;
		pll_rate = pix_rate * factor;

		dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",

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