Commit 515b2915 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: r8a77995: Correct parent clock of DU 



According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
of the DU module clocks on R-Car D3 is S1D1.

Fixes: d71e851d ("clk: renesas: cpg-mssr: Add R8A77995 support")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
parent 7cf3a216

drivers/clk/renesas/r8a77995-cpg-mssr.c

+2 −2
Original line number Diff line number Diff line
@@ -146,8 +146,8 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { 
	DEF_MOD("vspbs",		 627,	R8A77995_CLK_S0D1),

	DEF_MOD("ehci0",		 703,	R8A77995_CLK_S3D2),

	DEF_MOD("hsusb",		 704,	R8A77995_CLK_S3D2),

	DEF_MOD("du1",			 723,	R8A77995_CLK_S2D1),

	DEF_MOD("du0",			 724,	R8A77995_CLK_S2D1),

	DEF_MOD("du1",			 723,	R8A77995_CLK_S1D1),

	DEF_MOD("du0",			 724,	R8A77995_CLK_S1D1),

	DEF_MOD("lvds",			 727,	R8A77995_CLK_S2D1),

	DEF_MOD("vin7",			 804,	R8A77995_CLK_S1D2),

	DEF_MOD("vin6",			 805,	R8A77995_CLK_S1D2),

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