Commit 7cf3a216 authored Oct 12, 2018 by Takeshi Kihara Committed by Geert Uytterhoeven Dec 04, 2018

clk: renesas: r8a77990: Correct parent clock of DU



According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
of the DU module clocks on R-Car E3 is S1D1.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 3570a2af ("clk: renesas: cpg-mssr: Add support for R-Car E3")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

parent 396bc9d4

drivers/clk/renesas/r8a77990-cpg-mssr.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -183,8 +183,8 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
		DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
		DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
		DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
		DEF_MOD("du1", 723, R8A77990_CLK_S2D1),
		DEF_MOD("du0", 724, R8A77990_CLK_S2D1),
		DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
		DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
		DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),

		DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),

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