Commit 4f6cdf29 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branches 'for-next/acpi', 'for-next/cpufeatures', 'for-next/csum',... 

Merge branches 'for-next/acpi', 'for-next/cpufeatures', 'for-next/csum', 'for-next/e0pd', 'for-next/entry', 'for-next/kbuild', 'for-next/kexec/cleanup', 'for-next/kexec/file-kdump', 'for-next/misc', 'for-next/nofpsimd', 'for-next/perf' and 'for-next/scs' into for-next/core

* for-next/acpi:
  ACPI/IORT: Fix 'Number of IDs' handling in iort_id_map()

* for-next/cpufeatures: (2 commits)
  arm64: Introduce ID_ISAR6 CPU register
  ...

* for-next/csum: (2 commits)
  arm64: csum: Fix pathological zero-length calls
  ...

* for-next/e0pd: (7 commits)
  arm64: kconfig: Fix alignment of E0PD help text
  ...

* for-next/entry: (5 commits)
  arm64: entry: cleanup sp_el0 manipulation
  ...

* for-next/kbuild: (4 commits)
  arm64: kbuild: remove compressed images on 'make ARCH=arm64 (dist)clean'
  ...

* for-next/kexec/cleanup: (11 commits)
  Revert "arm64: kexec: make dtb_mem always enabled"
  ...

* for-next/kexec/file-kdump: (2 commits)
  arm64: kexec_file: add crash dump support
  ...

* for-next/misc: (12 commits)
  arm64: entry: Avoid empty alternatives entries
  ...

* for-next/nofpsimd: (7 commits)
  arm64: nofpsmid: Handle TIF_FOREIGN_FPSTATE flag cleanly
  ...

* for-next/perf: (2 commits)
  perf/imx_ddr: Fix cpu hotplug state cleanup
  ...

* for-next/scs: (6 commits)
  arm64: kernel: avoid x18 in __cpu_soft_restart
  ...
parents 3c23b83a 8e3747be c2c24edb e717d93b 3e393417 d7bbd6c1 1595fe29 3751e728 108eae2d 52f73c38 9ee68b31 500d14af

Documentation/arm64/cpu-feature-registers.rst

+14 −0
Original line number Diff line number Diff line
@@ -200,6 +200,12 @@ infrastructure: 
     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | I8MM                         | [55-52] |    y    |

     +------------------------------+---------+---------+

     | DGH                          | [51-48] |    y    |

     +------------------------------+---------+---------+

     | BF16                         | [47-44] |    y    |

     +------------------------------+---------+---------+

     | SB                           | [39-36] |    y    |

     +------------------------------+---------+---------+

     | FRINTTS                      | [35-32] |    y    |
@@ -234,10 +240,18 @@ infrastructure: 
     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | F64MM                        | [59-56] |    y    |

     +------------------------------+---------+---------+

     | F32MM                        | [55-52] |    y    |

     +------------------------------+---------+---------+

     | I8MM                         | [47-44] |    y    |

     +------------------------------+---------+---------+

     | SM4                          | [43-40] |    y    |

     +------------------------------+---------+---------+

     | SHA3                         | [35-32] |    y    |

     +------------------------------+---------+---------+

     | BF16                         | [23-20] |    y    |

     +------------------------------+---------+---------+

     | BitPerm                      | [19-16] |    y    |

     +------------------------------+---------+---------+

     | AES                          | [7-4]   |    y    |

Documentation/arm64/elf_hwcaps.rst

+27 −0
Original line number Diff line number Diff line
@@ -204,6 +204,33 @@ HWCAP2_FRINT 


    Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.



HWCAP2_SVEI8MM



    Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001.



HWCAP2_SVEF32MM



    Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001.



HWCAP2_SVEF64MM



    Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001.



HWCAP2_SVEBF16



    Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001.



HWCAP2_I8MM



    Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.



HWCAP2_BF16



    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0001.



HWCAP2_DGH



    Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001.



4. Unused AT_HWCAP bits

-----------------------

arch/arm64/Kconfig

+26 −1
Original line number Diff line number Diff line
@@ -161,6 +161,7 @@ config ARM64 
	select HAVE_PERF_USER_STACK_DUMP

	select HAVE_REGS_AND_STACK_ACCESS_API

	select HAVE_FUNCTION_ARG_ACCESS_API

	select HAVE_FUTEX_CMPXCHG if FUTEX

	select HAVE_RCU_TABLE_FREE

	select HAVE_RSEQ

	select HAVE_STACKPROTECTOR
@@ -301,6 +302,9 @@ config ARCH_SUPPORTS_UPROBES 
config ARCH_PROC_KCORE_TEXT

	def_bool y



config BROKEN_GAS_INST

	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)



config KASAN_SHADOW_OFFSET

	hex

	depends on KASAN
@@ -1363,6 +1367,11 @@ config ARM64_PAN 
	 instruction if the cpu does not implement the feature.



config ARM64_LSE_ATOMICS

	bool

	default ARM64_USE_LSE_ATOMICS

	depends on $(as-instr,.arch_extension lse)



config ARM64_USE_LSE_ATOMICS

	bool "Atomic instructions"

	depends on JUMP_LABEL

	default y
@@ -1484,6 +1493,22 @@ config ARM64_PTR_AUTH 


endmenu



menu "ARMv8.5 architectural features"



config ARM64_E0PD

	bool "Enable support for E0PD"

	default y

	help

	  E0PD (part of the ARMv8.5 extensions) allows us to ensure

	  that EL0 accesses made via TTBR1 always fault in constant time,

	  providing similar benefits to KASLR as those provided by KPTI, but

	  with lower overhead and without disrupting legitimate access to

	  kernel memory such as SPE.



	  This option enables E0PD for TTBR1 where available.



endmenu



config ARM64_SVE

	bool "ARM Scalable Vector Extension support"

	default y
@@ -1544,7 +1569,7 @@ config ARM64_MODULE_PLTS 


config ARM64_PSEUDO_NMI

	bool "Support for NMI-like interrupts"

	select CONFIG_ARM_GIC_V3

	select ARM_GIC_V3

	help

	  Adds support for mimicking Non-Maskable Interrupts through the use of

	  GIC interrupt priority. This support requires version 3 or later of

arch/arm64/Makefile

+5 −12
Original line number Diff line number Diff line
@@ -30,11 +30,8 @@ LDFLAGS_vmlinux += --fix-cortex-a53-843419 
  endif

endif



# Check for binutils support for specific extensions

lseinstr := $(call as-instr,.arch_extension lse,-DCONFIG_AS_LSE=1)



ifeq ($(CONFIG_ARM64_LSE_ATOMICS), y)

  ifeq ($(lseinstr),)

ifeq ($(CONFIG_ARM64_USE_LSE_ATOMICS), y)

  ifneq ($(CONFIG_ARM64_LSE_ATOMICS), y)

$(warning LSE atomics not supported by binutils)

  endif

endif
@@ -45,19 +42,15 @@ cc_has_k_constraint := $(call try-run,echo \ 
		return 0;						\

	}' | $(CC) -S -x c -o "$$TMP" -,,-DCONFIG_CC_HAS_K_CONSTRAINT=1)



ifeq ($(CONFIG_ARM64), y)

brokengasinst := $(call as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n,,-DCONFIG_BROKEN_GAS_INST=1)



  ifneq ($(brokengasinst),)

ifeq ($(CONFIG_BROKEN_GAS_INST),y)

$(warning Detected assembler with broken .inst; disassembly will be unreliable)

endif

endif



KBUILD_CFLAGS	+= -mgeneral-regs-only $(lseinstr) $(brokengasinst)	\

KBUILD_CFLAGS	+= -mgeneral-regs-only	\

		   $(compat_vdso) $(cc_has_k_constraint)

KBUILD_CFLAGS	+= -fno-asynchronous-unwind-tables

KBUILD_CFLAGS	+= $(call cc-disable-warning, psabi)

KBUILD_AFLAGS	+= $(lseinstr) $(brokengasinst) $(compat_vdso)

KBUILD_AFLAGS	+= $(compat_vdso)



KBUILD_CFLAGS	+= $(call cc-option,-mabi=lp64)

KBUILD_AFLAGS	+= $(call cc-option,-mabi=lp64)

arch/arm64/boot/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 


OBJCOPYFLAGS_Image :=-O binary -R .note -R .note.gnu.build-id -R .comment -S



targets := Image Image.gz

targets := Image Image.bz2 Image.gz Image.lz4 Image.lzma Image.lzo



$(obj)/Image: vmlinux FORCE

	$(call if_changed,objcopy)

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