Commit 4f5fd91f authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Remove I915_READ16 and I915_WRITE16 



Remove call sites in favour of uncore mmio accessors and remove the old
macros.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190611104548.30545-6-tvrtko.ursulin@linux.intel.com
parent 5a31d30b

drivers/gpu/drm/i915/gt/intel_ringbuffer.c

+3 −3
Original line number Diff line number Diff line
@@ -986,10 +986,10 @@ i8xx_irq_enable(struct intel_engine_cs *engine) 
static void

i8xx_irq_disable(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->i915;

	struct drm_i915_private *i915 = engine->i915;



	dev_priv->irq_mask |= engine->irq_enable_mask;

	I915_WRITE16(GEN2_IMR, dev_priv->irq_mask);

	i915->irq_mask |= engine->irq_enable_mask;

	intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask);

}



static int

drivers/gpu/drm/i915/i915_debugfs.c

+20 −17
Original line number Diff line number Diff line
@@ -826,6 +826,7 @@ static const struct file_operations i915_error_state_fops = { 
static int i915_frequency_info(struct seq_file *m, void *unused)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	struct intel_uncore *uncore = &dev_priv->uncore;

	struct intel_rps *rps = &dev_priv->gt_pm.rps;

	intel_wakeref_t wakeref;

	int ret = 0;
@@ -833,8 +834,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
	wakeref = intel_runtime_pm_get(dev_priv);



	if (IS_GEN(dev_priv, 5)) {

		u16 rgvswctl = I915_READ16(MEMSWCTL);

		u16 rgvstat = I915_READ16(MEMSTAT_ILK);

		u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);

		u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);



		seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);

		seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
@@ -1156,13 +1157,14 @@ static int i915_reset_info(struct seq_file *m, void *unused) 


static int ironlake_drpc_info(struct seq_file *m)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	struct drm_i915_private *i915 = node_to_i915(m->private);

	struct intel_uncore *uncore = &i915->uncore;

	u32 rgvmodectl, rstdbyctl;

	u16 crstandvid;



	rgvmodectl = I915_READ(MEMMODECTL);

	rstdbyctl = I915_READ(RSTDBYCTL);

	crstandvid = I915_READ16(CRSTANDVID);

	rgvmodectl = intel_uncore_read(uncore, MEMMODECTL);

	rstdbyctl = intel_uncore_read(uncore, RSTDBYCTL);

	crstandvid = intel_uncore_read16(uncore, CRSTANDVID);



	seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));

	seq_printf(m, "Boost freq: %d\n",
@@ -1745,6 +1747,7 @@ static const char *swizzle_string(unsigned swizzle) 
static int i915_swizzle_info(struct seq_file *m, void *data)

{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	struct intel_uncore *uncore = &dev_priv->uncore;

	intel_wakeref_t wakeref;



	wakeref = intel_runtime_pm_get(dev_priv);
@@ -1756,30 +1759,30 @@ static int i915_swizzle_info(struct seq_file *m, void *data) 


	if (IS_GEN_RANGE(dev_priv, 3, 4)) {

		seq_printf(m, "DDC = 0x%08x\n",

			   I915_READ(DCC));

			   intel_uncore_read(uncore, DCC));

		seq_printf(m, "DDC2 = 0x%08x\n",

			   I915_READ(DCC2));

			   intel_uncore_read(uncore, DCC2));

		seq_printf(m, "C0DRB3 = 0x%04x\n",

			   I915_READ16(C0DRB3));

			   intel_uncore_read16(uncore, C0DRB3));

		seq_printf(m, "C1DRB3 = 0x%04x\n",

			   I915_READ16(C1DRB3));

			   intel_uncore_read16(uncore, C1DRB3));

	} else if (INTEL_GEN(dev_priv) >= 6) {

		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",

			   I915_READ(MAD_DIMM_C0));

			   intel_uncore_read(uncore, MAD_DIMM_C0));

		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",

			   I915_READ(MAD_DIMM_C1));

			   intel_uncore_read(uncore, MAD_DIMM_C1));

		seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",

			   I915_READ(MAD_DIMM_C2));

			   intel_uncore_read(uncore, MAD_DIMM_C2));

		seq_printf(m, "TILECTL = 0x%08x\n",

			   I915_READ(TILECTL));

			   intel_uncore_read(uncore, TILECTL));

		if (INTEL_GEN(dev_priv) >= 8)

			seq_printf(m, "GAMTARBMODE = 0x%08x\n",

				   I915_READ(GAMTARBMODE));

				   intel_uncore_read(uncore, GAMTARBMODE));

		else

			seq_printf(m, "ARB_MODE = 0x%08x\n",

				   I915_READ(ARB_MODE));

				   intel_uncore_read(uncore, ARB_MODE));

		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",

			   I915_READ(DISP_ARB_CTL));

			   intel_uncore_read(uncore, DISP_ARB_CTL));

	}



	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)

drivers/gpu/drm/i915/i915_drv.h

+0 −3
Original line number Diff line number Diff line
@@ -2838,9 +2838,6 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 
#define __I915_REG_OP(op__, dev_priv__, ...) \

	intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)



#define I915_READ16(reg__)	   __I915_REG_OP(read16, dev_priv, (reg__))

#define I915_WRITE16(reg__, val__) __I915_REG_OP(write16, dev_priv, (reg__), (val__))



#define I915_READ(reg__)	 __I915_REG_OP(read, dev_priv, (reg__))

#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))

drivers/gpu/drm/i915/i915_gpu_error.c

+59 −45
Original line number Diff line number Diff line
@@ -1576,7 +1576,8 @@ static void capture_uc_state(struct i915_gpu_state *error) 
/* Capture all registers which don't fit into another category. */

static void capture_reg_state(struct i915_gpu_state *error)

{

	struct drm_i915_private *dev_priv = error->i915;

	struct drm_i915_private *i915 = error->i915;

	struct intel_uncore *uncore = &i915->uncore;

	int i;



	/* General organization
@@ -1588,71 +1589,84 @@ static void capture_reg_state(struct i915_gpu_state *error) 
	 */



	/* 1: Registers specific to a single generation */

	if (IS_VALLEYVIEW(dev_priv)) {

		error->gtier[0] = I915_READ(GTIER);

		error->ier = I915_READ(VLV_IER);

		error->forcewake = I915_READ_FW(FORCEWAKE_VLV);

	if (IS_VALLEYVIEW(i915)) {

		error->gtier[0] = intel_uncore_read(uncore, GTIER);

		error->ier = intel_uncore_read(uncore, VLV_IER);

		error->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);

	}



	if (IS_GEN(dev_priv, 7))

		error->err_int = I915_READ(GEN7_ERR_INT);

	if (IS_GEN(i915, 7))

		error->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);



	if (INTEL_GEN(dev_priv) >= 8) {

		error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);

		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);

	if (INTEL_GEN(i915) >= 8) {

		error->fault_data0 = intel_uncore_read(uncore,

						       GEN8_FAULT_TLB_DATA0);

		error->fault_data1 = intel_uncore_read(uncore,

						       GEN8_FAULT_TLB_DATA1);

	}



	if (IS_GEN(dev_priv, 6)) {

		error->forcewake = I915_READ_FW(FORCEWAKE);

		error->gab_ctl = I915_READ(GAB_CTL);

		error->gfx_mode = I915_READ(GFX_MODE);

	if (IS_GEN(i915, 6)) {

		error->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);

		error->gab_ctl = intel_uncore_read(uncore, GAB_CTL);

		error->gfx_mode = intel_uncore_read(uncore, GFX_MODE);

	}



	/* 2: Registers which belong to multiple generations */

	if (INTEL_GEN(dev_priv) >= 7)

		error->forcewake = I915_READ_FW(FORCEWAKE_MT);

	if (INTEL_GEN(i915) >= 7)

		error->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);



	if (INTEL_GEN(dev_priv) >= 6) {

		error->derrmr = I915_READ(DERRMR);

		error->error = I915_READ(ERROR_GEN6);

		error->done_reg = I915_READ(DONE_REG);

	if (INTEL_GEN(i915) >= 6) {

		error->derrmr = intel_uncore_read(uncore, DERRMR);

		error->error = intel_uncore_read(uncore, ERROR_GEN6);

		error->done_reg = intel_uncore_read(uncore, DONE_REG);

	}



	if (INTEL_GEN(dev_priv) >= 5)

		error->ccid = I915_READ(CCID(RENDER_RING_BASE));

	if (INTEL_GEN(i915) >= 5)

		error->ccid = intel_uncore_read(uncore, CCID(RENDER_RING_BASE));



	/* 3: Feature specific registers */

	if (IS_GEN_RANGE(dev_priv, 6, 7)) {

		error->gam_ecochk = I915_READ(GAM_ECOCHK);

		error->gac_eco = I915_READ(GAC_ECO_BITS);

	if (IS_GEN_RANGE(i915, 6, 7)) {

		error->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);

		error->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);

	}



	/* 4: Everything else */

	if (INTEL_GEN(dev_priv) >= 11) {

		error->ier = I915_READ(GEN8_DE_MISC_IER);

		error->gtier[0] = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);

		error->gtier[1] = I915_READ(GEN11_VCS_VECS_INTR_ENABLE);

		error->gtier[2] = I915_READ(GEN11_GUC_SG_INTR_ENABLE);

		error->gtier[3] = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);

		error->gtier[4] = I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE);

		error->gtier[5] = I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE);

	if (INTEL_GEN(i915) >= 11) {

		error->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);

		error->gtier[0] =

			intel_uncore_read(uncore,

					  GEN11_RENDER_COPY_INTR_ENABLE);

		error->gtier[1] =

			intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE);

		error->gtier[2] =

			intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE);

		error->gtier[3] =

			intel_uncore_read(uncore,

					  GEN11_GPM_WGBOXPERF_INTR_ENABLE);

		error->gtier[4] =

			intel_uncore_read(uncore,

					  GEN11_CRYPTO_RSVD_INTR_ENABLE);

		error->gtier[5] =

			intel_uncore_read(uncore,

					  GEN11_GUNIT_CSME_INTR_ENABLE);

		error->ngtier = 6;

	} else if (INTEL_GEN(dev_priv) >= 8) {

		error->ier = I915_READ(GEN8_DE_MISC_IER);

	} else if (INTEL_GEN(i915) >= 8) {

		error->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);

		for (i = 0; i < 4; i++)

			error->gtier[i] = I915_READ(GEN8_GT_IER(i));

			error->gtier[i] = intel_uncore_read(uncore,

							    GEN8_GT_IER(i));

		error->ngtier = 4;

	} else if (HAS_PCH_SPLIT(dev_priv)) {

		error->ier = I915_READ(DEIER);

		error->gtier[0] = I915_READ(GTIER);

	} else if (HAS_PCH_SPLIT(i915)) {

		error->ier = intel_uncore_read(uncore, DEIER);

		error->gtier[0] = intel_uncore_read(uncore, GTIER);

		error->ngtier = 1;

	} else if (IS_GEN(dev_priv, 2)) {

		error->ier = I915_READ16(GEN2_IER);

	} else if (!IS_VALLEYVIEW(dev_priv)) {

		error->ier = I915_READ(GEN2_IER);

	} else if (IS_GEN(i915, 2)) {

		error->ier = intel_uncore_read16(uncore, GEN2_IER);

	} else if (!IS_VALLEYVIEW(i915)) {

		error->ier = intel_uncore_read(uncore, GEN2_IER);

	}

	error->eir = I915_READ(EIR);

	error->pgtbl_er = I915_READ(PGTBL_ER);

	error->eir = intel_uncore_read(uncore, EIR);

	error->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);

}



static const char *

drivers/gpu/drm/i915/i915_irq.c

+23 −17
Original line number Diff line number Diff line
@@ -1232,20 +1232,23 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc) 


static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;

	u32 busy_up, busy_down, max_avg, min_avg;

	u8 new_delay;



	spin_lock(&mchdev_lock);



	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));

	intel_uncore_write16(uncore,

			     MEMINTRSTS,

			     intel_uncore_read(uncore, MEMINTRSTS));



	new_delay = dev_priv->ips.cur_delay;



	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);

	busy_up = I915_READ(RCPREVBSYTUPAVG);

	busy_down = I915_READ(RCPREVBSYTDNAVG);

	max_avg = I915_READ(RCBMAXAVG);

	min_avg = I915_READ(RCBMINAVG);

	intel_uncore_write16(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);

	busy_up = intel_uncore_read(uncore, RCPREVBSYTUPAVG);

	busy_down = intel_uncore_read(uncore, RCPREVBSYTDNAVG);

	max_avg = intel_uncore_read(uncore, RCBMAXAVG);

	min_avg = intel_uncore_read(uncore, RCBMINAVG);



	/* Handle RCS change request from hw */

	if (busy_up > max_avg) {
@@ -4324,7 +4327,9 @@ static int i8xx_irq_postinstall(struct drm_device *dev) 
	struct intel_uncore *uncore = &dev_priv->uncore;

	u16 enable_mask;



	I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE |

	intel_uncore_write16(uncore,

			     EMR,

			     ~(I915_ERROR_PAGE_TABLE |

			       I915_ERROR_MEMORY_REFRESH));



	/* Unmask the interrupts that we always want on. */
@@ -4351,17 +4356,18 @@ static int i8xx_irq_postinstall(struct drm_device *dev) 
	return 0;

}



static void i8xx_error_irq_ack(struct drm_i915_private *dev_priv,

static void i8xx_error_irq_ack(struct drm_i915_private *i915,

			       u16 *eir, u16 *eir_stuck)

{

	struct intel_uncore *uncore = &i915->uncore;

	u16 emr;



	*eir = I915_READ16(EIR);

	*eir = intel_uncore_read16(uncore, EIR);



	if (*eir)

		I915_WRITE16(EIR, *eir);

		intel_uncore_write16(uncore, EIR, *eir);



	*eir_stuck = I915_READ16(EIR);

	*eir_stuck = intel_uncore_read16(uncore, EIR);

	if (*eir_stuck == 0)

		return;
@@ -4375,9 +4381,9 @@ static void i8xx_error_irq_ack(struct drm_i915_private *dev_priv, 
	 * (or by a GPU reset) so we mask any bit that

	 * remains set.

	 */

	emr = I915_READ16(EMR);

	I915_WRITE16(EMR, 0xffff);

	I915_WRITE16(EMR, emr | *eir_stuck);

	emr = intel_uncore_read16(uncore, EMR);

	intel_uncore_write16(uncore, EMR, 0xffff);

	intel_uncore_write16(uncore, EMR, emr | *eir_stuck);

}



static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
@@ -4443,7 +4449,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) 
		u16 eir = 0, eir_stuck = 0;

		u16 iir;



		iir = I915_READ16(GEN2_IIR);

		iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);

		if (iir == 0)

			break;
@@ -4456,7 +4462,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) 
		if (iir & I915_MASTER_ERROR_INTERRUPT)

			i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);



		I915_WRITE16(GEN2_IIR, iir);

		intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);



		if (iir & I915_USER_INTERRUPT)

			intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);

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