Commit 5a31d30b authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Remove I915_READ_NOTRACE 



Only a few call sites remain which have been converted to uncore mmio
accessors and so the macro can be removed.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190611104548.30545-5-tvrtko.ursulin@linux.intel.com
parent 54ac6479

drivers/gpu/drm/i915/gvt/debugfs.c

+2 −2
Original line number Diff line number Diff line
@@ -58,12 +58,12 @@ static int mmio_offset_compare(void *priv, 
static inline int mmio_diff_handler(struct intel_gvt *gvt,

				    u32 offset, void *data)

{

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct drm_i915_private *i915 = gvt->dev_priv;

	struct mmio_diff_param *param = data;

	struct diff_mmio *node;

	u32 preg, vreg;



	preg = I915_READ_NOTRACE(_MMIO(offset));

	preg = intel_uncore_read_notrace(&i915->uncore, _MMIO(offset));

	vreg = vgpu_vreg(param->vgpu, offset);



	if (preg != vreg) {

drivers/gpu/drm/i915/gvt/firmware.c

+3 −2
Original line number Diff line number Diff line
@@ -68,9 +68,10 @@ static struct bin_attribute firmware_attr = { 


static int mmio_snapshot_handler(struct intel_gvt *gvt, u32 offset, void *data)

{

	struct drm_i915_private *dev_priv = gvt->dev_priv;

	struct drm_i915_private *i915 = gvt->dev_priv;



	*(u32 *)(data + offset) = I915_READ_NOTRACE(_MMIO(offset));

	*(u32 *)(data + offset) = intel_uncore_read_notrace(&i915->uncore,

							    _MMIO(offset));

	return 0;

}

drivers/gpu/drm/i915/i915_drv.c

+4 −2
Original line number Diff line number Diff line
@@ -2708,7 +2708,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) 
	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);

}



static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,

static int vlv_wait_for_pw_status(struct drm_i915_private *i915,

				  u32 mask, u32 val)

{

	i915_reg_t reg = VLV_GTLC_PW_STATUS;
@@ -2722,7 +2722,9 @@ static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv, 
	 * Transitioning between RC6 states should be at most 2ms (see

	 * valleyview_enable_rps) so use a 3ms timeout.

	 */

	ret = wait_for(((reg_value = I915_READ_NOTRACE(reg)) & mask) == val, 3);

	ret = wait_for(((reg_value =

			 intel_uncore_read_notrace(&i915->uncore, reg)) & mask)

		       == val, 3);



	/* just trace the final value */

	trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);

drivers/gpu/drm/i915/i915_drv.h

+0 −1
Original line number Diff line number Diff line
@@ -2843,7 +2843,6 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 


#define I915_READ(reg__)	 __I915_REG_OP(read, dev_priv, (reg__))

#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))

#define I915_READ_NOTRACE(reg__)	 __I915_REG_OP(read_notrace, dev_priv, (reg__))



#define POSTING_READ(reg__)	__I915_REG_OP(posting_read, dev_priv, (reg__))

drivers/gpu/drm/i915/i915_pmu.c

+5 −3
Original line number Diff line number Diff line
@@ -227,9 +227,11 @@ frequency_sample(struct drm_i915_private *dev_priv, unsigned int period_ns) 
		if (dev_priv->gt.awake) {

			intel_wakeref_t wakeref;



			with_intel_runtime_pm_if_in_use(dev_priv, wakeref)

				val = intel_get_cagf(dev_priv,

						     I915_READ_NOTRACE(GEN6_RPSTAT1));

			with_intel_runtime_pm_if_in_use(dev_priv, wakeref) {

				val = intel_uncore_read_notrace(&dev_priv->uncore,

								GEN6_RPSTAT1);

				val = intel_get_cagf(dev_priv, val);

			}

		}



		add_sample_mult(&dev_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT],

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