Commit 4d130238 authored by Monk Liu's avatar Monk Liu Committed by Alex Deucher
Browse files

drm/amdgpu: cleanup idh event/req for NV headers 



1) drop the headers from AI in mxgpu_nv.c, should refer to mxgpu_nv.h

2) the IDH_EVENT_MAX is not used and not aligned with host side
   so drop it
3) the IDH_TEXT_MESSAG was provided in host but not defined in guest

Signed-off-by: default avatarMonk Liu <Monk.Liu@amd.com>
Reviewed-by: default avatarEmily Deng <Emily.Deng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ba56657d

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h

+2 −1
Original line number Diff line number Diff line
@@ -46,7 +46,8 @@ enum idh_event { 
	IDH_SUCCESS,

	IDH_FAIL,

	IDH_QUERY_ALIVE,

	IDH_EVENT_MAX



	IDH_TEXT_MESSAGE = 255,

};



extern const struct amdgpu_virt_ops xgpu_ai_virt_ops;

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c

+0 −1
Original line number Diff line number Diff line
@@ -30,7 +30,6 @@ 
#include "navi10_ih.h"

#include "soc15_common.h"

#include "mxgpu_nv.h"

#include "mxgpu_ai.h"



static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev)

{

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h

+22 −0
Original line number Diff line number Diff line
@@ -28,6 +28,28 @@ 
#define NV_MAILBOX_POLL_MSG_TIMEDOUT	12000

#define NV_MAILBOX_POLL_FLR_TIMEDOUT	500



enum idh_request {

	IDH_REQ_GPU_INIT_ACCESS = 1,

	IDH_REL_GPU_INIT_ACCESS,

	IDH_REQ_GPU_FINI_ACCESS,

	IDH_REL_GPU_FINI_ACCESS,

	IDH_REQ_GPU_RESET_ACCESS,



	IDH_LOG_VF_ERROR       = 200,

};



enum idh_event {

	IDH_CLR_MSG_BUF	= 0,

	IDH_READY_TO_ACCESS_GPU,

	IDH_FLR_NOTIFICATION,

	IDH_FLR_NOTIFICATION_CMPL,

	IDH_SUCCESS,

	IDH_FAIL,

	IDH_QUERY_ALIVE,



	IDH_TEXT_MESSAGE = 255,

};



extern const struct amdgpu_virt_ops xgpu_nv_virt_ops;



void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h

+2 −1
Original line number Diff line number Diff line
@@ -43,7 +43,8 @@ enum idh_event { 
	IDH_READY_TO_ACCESS_GPU,

	IDH_FLR_NOTIFICATION,

	IDH_FLR_NOTIFICATION_CMPL,

	IDH_EVENT_MAX



	IDH_TEXT_MESSAGE = 255

};



extern const struct amdgpu_virt_ops xgpu_vi_virt_ops;

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