Commit 4cb3b44d authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: Wrappers for display register waits 



To reduce the number of explicit dev_priv->uncore calls in the display
code ahead of the introduction of dev_priv->de_uncore, this patch
introduces a wrapper for one of the main usages of it, the register
waits. When we transition to the new uncore, we can just update the
wrapper to point to the appropriate structure.

Since the vast majority of waits are on a set or clear of a bit or mask,
add set & clear flavours of the wrapper to simplify the code.

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190816012343.36433-7-daniele.ceraolospurio@intel.com
parent 4e3f12d8

drivers/gpu/drm/i915/display/icl_dsi.c

+4 −7
Original line number Diff line number Diff line
@@ -898,9 +898,7 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 
		I915_WRITE(PIPECONF(dsi_trans), tmp);



		/* wait for transcoder to be enabled */

		if (intel_wait_for_register(&dev_priv->uncore,

					    PIPECONF(dsi_trans),

					    I965_PIPECONF_ACTIVE,

		if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),

					  I965_PIPECONF_ACTIVE, 10))

			DRM_ERROR("DSI transcoder not enabled\n");

	}
@@ -1080,9 +1078,8 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 
		I915_WRITE(PIPECONF(dsi_trans), tmp);



		/* wait for transcoder to be disabled */

		if (intel_wait_for_register(&dev_priv->uncore,

					    PIPECONF(dsi_trans),

					    I965_PIPECONF_ACTIVE, 0, 50))

		if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),

					    I965_PIPECONF_ACTIVE, 50))

			DRM_ERROR("DSI trancoder not disabled\n");

	}

}

drivers/gpu/drm/i915/display/intel_cdclk.c

+6 −14
Original line number Diff line number Diff line
@@ -969,9 +969,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 


	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);



	if (intel_wait_for_register(&dev_priv->uncore,

				    LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,

				    5))

	if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))

		DRM_ERROR("DPLL0 not locked\n");



	dev_priv->cdclk.hw.vco = vco;
@@ -983,9 +981,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 
static void skl_dpll0_disable(struct drm_i915_private *dev_priv)

{

	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);

	if (intel_wait_for_register(&dev_priv->uncore,

				    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,

				    1))

	if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))

		DRM_ERROR("Couldn't disable DPLL0\n");



	dev_priv->cdclk.hw.vco = 0;
@@ -1309,9 +1305,8 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 
	I915_WRITE(BXT_DE_PLL_ENABLE, 0);



	/* Timeout 200us */

	if (intel_wait_for_register(&dev_priv->uncore,

				    BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,

				    1))

	if (intel_de_wait_for_clear(dev_priv,

				    BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))

		DRM_ERROR("timeout waiting for DE PLL unlock\n");



	dev_priv->cdclk.hw.vco = 0;
@@ -1330,11 +1325,8 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 
	I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);



	/* Timeout 200us */

	if (intel_wait_for_register(&dev_priv->uncore,

				    BXT_DE_PLL_ENABLE,

				    BXT_DE_PLL_LOCK,

				    BXT_DE_PLL_LOCK,

				    1))

	if (intel_de_wait_for_set(dev_priv,

				  BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))

		DRM_ERROR("timeout waiting for DE PLL lock\n");



	dev_priv->cdclk.hw.vco = vco;

drivers/gpu/drm/i915/display/intel_crt.c

+6 −9
Original line number Diff line number Diff line
@@ -443,9 +443,9 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 


		I915_WRITE(crt->adpa_reg, adpa);



		if (intel_wait_for_register(&dev_priv->uncore,

		if (intel_de_wait_for_clear(dev_priv,

					    crt->adpa_reg,

					    ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,

					    ADPA_CRT_HOTPLUG_FORCE_TRIGGER,

					    1000))

			DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
@@ -497,10 +497,8 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 


	I915_WRITE(crt->adpa_reg, adpa);



	if (intel_wait_for_register(&dev_priv->uncore,

				    crt->adpa_reg,

				    ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,

				    1000)) {

	if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,

				    ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {

		DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");

		I915_WRITE(crt->adpa_reg, save_adpa);

	}
@@ -550,9 +548,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) 
					      CRT_HOTPLUG_FORCE_DETECT,

					      CRT_HOTPLUG_FORCE_DETECT);

		/* wait for FORCE_DETECT to go off */

		if (intel_wait_for_register(&dev_priv->uncore, PORT_HOTPLUG_EN,

					    CRT_HOTPLUG_FORCE_DETECT, 0,

					    1000))

		if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,

					    CRT_HOTPLUG_FORCE_DETECT, 1000))

			DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");

	}

drivers/gpu/drm/i915/display/intel_ddi.c

+2 −4
Original line number Diff line number Diff line
@@ -3139,10 +3139,8 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder, 
	val |= DP_TP_CTL_FEC_ENABLE;

	I915_WRITE(DP_TP_CTL(port), val);



	if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),

				    DP_TP_STATUS_FEC_ENABLE_LIVE,

				    DP_TP_STATUS_FEC_ENABLE_LIVE,

				    1))

	if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),

				  DP_TP_STATUS_FEC_ENABLE_LIVE, 1))

		DRM_ERROR("Timed out waiting for FEC Enable Status\n");

}

drivers/gpu/drm/i915/display/intel_display.c

+14 −34
Original line number Diff line number Diff line
@@ -1077,9 +1077,8 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 
		i915_reg_t reg = PIPECONF(cpu_transcoder);



		/* Wait for the Pipe State to go off */

		if (intel_wait_for_register(&dev_priv->uncore,

					    reg, I965_PIPECONF_ACTIVE, 0,

					    100))

		if (intel_de_wait_for_clear(dev_priv, reg,

					    I965_PIPECONF_ACTIVE, 100))

			WARN(1, "pipe_off wait timed out\n");

	} else {

		intel_wait_for_pipe_scanline_stopped(crtc);
@@ -1383,11 +1382,7 @@ static void _vlv_enable_pll(struct intel_crtc *crtc, 
	POSTING_READ(DPLL(pipe));

	udelay(150);



	if (intel_wait_for_register(&dev_priv->uncore,

				    DPLL(pipe),

				    DPLL_LOCK_VLV,

				    DPLL_LOCK_VLV,

				    1))

	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))

		DRM_ERROR("DPLL %d failed to lock\n", pipe);

}
@@ -1436,9 +1431,7 @@ static void _chv_enable_pll(struct intel_crtc *crtc, 
	I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);



	/* Check PLL is locked */

	if (intel_wait_for_register(&dev_priv->uncore,

				    DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,

				    1))

	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))

		DRM_ERROR("PLL %d failed to lock\n", pipe);

}
@@ -1617,9 +1610,8 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 
		BUG();

	}



	if (intel_wait_for_register(&dev_priv->uncore,

				    dpll_reg, port_mask, expected_mask,

				    1000))

	if (intel_de_wait_for_register(dev_priv, dpll_reg,

				       port_mask, expected_mask, 1000))

		WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",

		     port_name(dport->base.port),

		     I915_READ(dpll_reg) & port_mask, expected_mask);
@@ -1678,9 +1670,7 @@ static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s 
	}



	I915_WRITE(reg, val | TRANS_ENABLE);

	if (intel_wait_for_register(&dev_priv->uncore,

				    reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,

				    100))

	if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))

		DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));

}
@@ -1708,11 +1698,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, 
		val |= TRANS_PROGRESSIVE;



	I915_WRITE(LPT_TRANSCONF, val);

	if (intel_wait_for_register(&dev_priv->uncore,

				    LPT_TRANSCONF,

				    TRANS_STATE_ENABLE,

				    TRANS_STATE_ENABLE,

				    100))

	if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,

				  TRANS_STATE_ENABLE, 100))

		DRM_ERROR("Failed to enable PCH transcoder\n");

}
@@ -1734,9 +1721,7 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, 
	val &= ~TRANS_ENABLE;

	I915_WRITE(reg, val);

	/* wait for PCH transcoder off, transcoder state */

	if (intel_wait_for_register(&dev_priv->uncore,

				    reg, TRANS_STATE_ENABLE, 0,

				    50))

	if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))

		DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));



	if (HAS_PCH_CPT(dev_priv)) {
@@ -1756,9 +1741,8 @@ void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) 
	val &= ~TRANS_ENABLE;

	I915_WRITE(LPT_TRANSCONF, val);

	/* wait for PCH transcoder off, transcoder state */

	if (intel_wait_for_register(&dev_priv->uncore,

				    LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,

				    50))

	if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,

				    TRANS_STATE_ENABLE, 50))

		DRM_ERROR("Failed to disable PCH transcoder\n");



	/* Workaround: clear timing override bit. */
@@ -5697,9 +5681,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) 
		 * and don't wait for vblanks until the end of crtc_enable, then

		 * the HW state readout code will complain that the expected

		 * IPS_CTL value is not the one we read. */

		if (intel_wait_for_register(&dev_priv->uncore,

					    IPS_CTL, IPS_ENABLE, IPS_ENABLE,

					    50))

		if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))

			DRM_ERROR("Timed out waiting for IPS enable\n");

	}

}
@@ -5720,9 +5702,7 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state) 
		 * 42ms timeout value leads to occasional timeouts so use 100ms

		 * instead.

		 */

		if (intel_wait_for_register(&dev_priv->uncore,

					    IPS_CTL, IPS_ENABLE, 0,

					    100))

		if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))

			DRM_ERROR("Timed out waiting for IPS disable\n");

	} else {

		I915_WRITE(IPS_CTL, 0);

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