Commit 4e3f12d8 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: Move gmbus definitions out of i915_reg.h 



They're not related to registers, so move them to the more appropriate
intel_gmbus.h

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190816012343.36433-4-daniele.ceraolospurio@intel.com
parent 3d7b3039

drivers/gpu/drm/i915/display/intel_gmbus.h

+22 −0
Original line number Diff line number Diff line
@@ -11,6 +11,28 @@ 
struct drm_i915_private;

struct i2c_adapter;



#define GMBUS_PIN_DISABLED	0

#define GMBUS_PIN_SSC		1

#define GMBUS_PIN_VGADDC	2

#define GMBUS_PIN_PANEL		3

#define GMBUS_PIN_DPD_CHV	3 /* HDMID_CHV */

#define GMBUS_PIN_DPC		4 /* HDMIC */

#define GMBUS_PIN_DPB		5 /* SDVO, HDMIB */

#define GMBUS_PIN_DPD		6 /* HDMID */

#define GMBUS_PIN_RESERVED	7 /* 7 reserved */

#define GMBUS_PIN_1_BXT		1 /* BXT+ (atom) and CNP+ (big core) */

#define GMBUS_PIN_2_BXT		2

#define GMBUS_PIN_3_BXT		3

#define GMBUS_PIN_4_CNP		4

#define GMBUS_PIN_9_TC1_ICP	9

#define GMBUS_PIN_10_TC2_ICP	10

#define GMBUS_PIN_11_TC3_ICP	11

#define GMBUS_PIN_12_TC4_ICP	12

#define GMBUS_PIN_13_TC5_TGP	13

#define GMBUS_PIN_14_TC6_TGP	14



#define GMBUS_NUM_PINS	15 /* including 0 */



int intel_gmbus_setup(struct drm_i915_private *dev_priv);

void intel_gmbus_teardown(struct drm_i915_private *dev_priv);

bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ 
#include "display/intel_display_power.h"

#include "display/intel_dpll_mgr.h"

#include "display/intel_frontbuffer.h"

#include "display/intel_gmbus.h"

#include "display/intel_opregion.h"



#include "gem/i915_gem_context_types.h"

drivers/gpu/drm/i915/i915_reg.h

+1 −21
Original line number Diff line number Diff line
@@ -3207,27 +3207,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   GMBUS_RATE_1MHZ	(3 << 8) /* reserved on Pineview */

#define   GMBUS_HOLD_EXT	(1 << 7) /* 300ns hold time, rsvd on Pineview */

#define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)

#define   GMBUS_PIN_DISABLED	0

#define   GMBUS_PIN_SSC		1

#define   GMBUS_PIN_VGADDC	2

#define   GMBUS_PIN_PANEL	3

#define   GMBUS_PIN_DPD_CHV	3 /* HDMID_CHV */

#define   GMBUS_PIN_DPC		4 /* HDMIC */

#define   GMBUS_PIN_DPB		5 /* SDVO, HDMIB */

#define   GMBUS_PIN_DPD		6 /* HDMID */

#define   GMBUS_PIN_RESERVED	7 /* 7 reserved */

#define   GMBUS_PIN_1_BXT	1 /* BXT+ (atom) and CNP+ (big core) */

#define   GMBUS_PIN_2_BXT	2

#define   GMBUS_PIN_3_BXT	3

#define   GMBUS_PIN_4_CNP	4

#define   GMBUS_PIN_9_TC1_ICP	9

#define   GMBUS_PIN_10_TC2_ICP	10

#define   GMBUS_PIN_11_TC3_ICP	11

#define   GMBUS_PIN_12_TC4_ICP	12

#define   GMBUS_PIN_13_TC5_TGP	13

#define   GMBUS_PIN_14_TC6_TGP	14



#define   GMBUS_NUM_PINS	15 /* including 0 */



#define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */

#define   GMBUS_SW_CLR_INT	(1 << 31)

#define   GMBUS_SW_RDY		(1 << 30)

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