Commit 4c6a8fe3 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/dwc' 

  - Add intel-gw driver for PCIe host controller on Intel Gateway SoC
    (Dilip Kota)

  - Use shared DesignWare helpers to configure Fast Training Sequence (FTS)
    in artpec6 (Dilip Kota)

* remotes/lorenzo/pci/dwc:
  PCI: artpec6: Configure FTS with dwc helper function
  PCI: dwc: intel: PCIe RC controller driver
  dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
parents 61d02c37 6fd622c2

Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml

0 → 100644
+138 −0
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: PCIe RC controller on Intel Gateway SoCs



maintainers:

  - Dilip Kota <eswara.kota@linux.intel.com>



properties:

  compatible:

    items:

      - const: intel,lgm-pcie

      - const: snps,dw-pcie



  device_type:

    const: pci



  "#address-cells":

    const: 3



  "#size-cells":

    const: 2



  reg:

    items:

      - description: Controller control and status registers.

      - description: PCIe configuration registers.

      - description: Controller application registers.



  reg-names:

    items:

      - const: dbi

      - const: config

      - const: app



  ranges:

    maxItems: 1



  resets:

    maxItems: 1



  clocks:

    maxItems: 1



  phys:

    maxItems: 1



  phy-names:

    const: pcie



  reset-gpios:

    maxItems: 1



  linux,pci-domain: true



  num-lanes:

    maximum: 2

    description: Number of lanes to use for this port.



  '#interrupt-cells':

    const: 1



  interrupt-map-mask:

    description: Standard PCI IRQ mapping properties.



  interrupt-map:

    description: Standard PCI IRQ mapping properties.



  max-link-speed:

    description: Specify PCI Gen for link capability.

    allOf:

      - $ref: /schemas/types.yaml#/definitions/uint32

      - enum: [ 1, 2, 3, 4 ]

      - default: 1



  bus-range:

    description: Range of bus numbers associated with this controller.



  reset-assert-ms:

    description: |

      Delay after asserting reset to the PCIe device.

    maximum: 500

    default: 100



required:

  - compatible

  - device_type

  - "#address-cells"

  - "#size-cells"

  - reg

  - reg-names

  - ranges

  - resets

  - clocks

  - phys

  - phy-names

  - reset-gpios

  - '#interrupt-cells'

  - interrupt-map

  - interrupt-map-mask



additionalProperties: false



examples:

  - |

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/clock/intel,lgm-clk.h>

    pcie10: pcie@d0e00000 {

      compatible = "intel,lgm-pcie", "snps,dw-pcie";

      device_type = "pci";

      #address-cells = <3>;

      #size-cells = <2>;

      reg = <0xd0e00000 0x1000>,

            <0xd2000000 0x800000>,

            <0xd0a41000 0x1000>;

      reg-names = "dbi", "config", "app";

      linux,pci-domain = <0>;

      max-link-speed = <4>;

      bus-range = <0x00 0x08>;

      interrupt-parent = <&ioapic1>;

      #interrupt-cells = <1>;

      interrupt-map-mask = <0 0 0 0x7>;

      interrupt-map = <0 0 0 1 &ioapic1 27 1>,

                      <0 0 0 2 &ioapic1 28 1>,

                      <0 0 0 3 &ioapic1 29 1>,

                      <0 0 0 4 &ioapic1 30 1>;

      ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;

      resets = <&rcu0 0x50 0>;

      clocks = <&cgu0 LGM_GCLK_PCIE10>;

      phys = <&cb0phy0>;

      phy-names = "pcie";

      reset-assert-ms = <500>;

      reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;

      num-lanes = <2>;

    };

drivers/pci/controller/dwc/Kconfig

+11 −0
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@@ -209,6 +209,17 @@ config PCIE_ARTPEC6_EP 
	  Enables support for the PCIe controller in the ARTPEC-6 SoC to work in

	  endpoint mode. This uses the DesignWare core.



config PCIE_INTEL_GW

	bool "Intel Gateway PCIe host controller support"

	depends on OF && (X86 || COMPILE_TEST)

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIE_DW_HOST

	help

	  Say 'Y' here to enable PCIe Host controller support on Intel

	  Gateway SoCs.

	  The PCIe controller uses the DesignWare core plus Intel-specific

	  hardware wrappers.



config PCIE_KIRIN

	depends on OF && (ARM64 || COMPILE_TEST)

	bool "HiSilicon Kirin series SoCs PCIe controllers"

drivers/pci/controller/dwc/Makefile

+1 −0
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@@ -13,6 +13,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o 
obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o

obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o

obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o

obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o

obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o

obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o

obj-$(CONFIG_PCI_MESON) += pci-meson.o

drivers/pci/controller/dwc/pcie-artpec6.c

+1 −7
Original line number Diff line number Diff line
@@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[]; 
#define ACK_N_FTS_MASK			GENMASK(15, 8)

#define ACK_N_FTS(x)			(((x) << 8) & ACK_N_FTS_MASK)



#define FAST_TRAINING_SEQ_MASK		GENMASK(7, 0)

#define FAST_TRAINING_SEQ(x)		(((x) << 0) & FAST_TRAINING_SEQ_MASK)



/* ARTPEC-6 specific registers */

#define PCIECFG				0x18

#define  PCIECFG_DBG_OEN		BIT(24)
@@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie) 
	 * Set the Number of Fast Training Sequences that the core

	 * advertises as its N_FTS during Gen2 or Gen3 link training.

	 */

	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);

	val &= ~FAST_TRAINING_SEQ_MASK;

	val |= FAST_TRAINING_SEQ(180);

	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);

	dw_pcie_link_set_n_fts(pci, 180);

}



static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)

drivers/pci/controller/dwc/pcie-designware.c

+56 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/of.h>

#include <linux/types.h>



#include "../../pci.h"

#include "pcie-designware.h"



/*
@@ -474,6 +475,61 @@ int dw_pcie_link_up(struct dw_pcie *pci) 
		(!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));

}



void dw_pcie_upconfig_setup(struct dw_pcie *pci)

{

	u32 val;



	val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);

	val |= PORT_MLTI_UPCFG_SUPPORT;

	dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);

}

EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);



void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)

{

	u32 reg, val;

	u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);



	reg = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);

	reg &= ~PCI_EXP_LNKCTL2_TLS;



	switch (pcie_link_speed[link_gen]) {

	case PCIE_SPEED_2_5GT:

		reg |= PCI_EXP_LNKCTL2_TLS_2_5GT;

		break;

	case PCIE_SPEED_5_0GT:

		reg |= PCI_EXP_LNKCTL2_TLS_5_0GT;

		break;

	case PCIE_SPEED_8_0GT:

		reg |= PCI_EXP_LNKCTL2_TLS_8_0GT;

		break;

	case PCIE_SPEED_16_0GT:

		reg |= PCI_EXP_LNKCTL2_TLS_16_0GT;

		break;

	default:

		/* Use hardware capability */

		val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);

		val = FIELD_GET(PCI_EXP_LNKCAP_SLS, val);

		reg &= ~PCI_EXP_LNKCTL2_HASD;

		reg |= FIELD_PREP(PCI_EXP_LNKCTL2_TLS, val);

		break;

	}



	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, reg);

}

EXPORT_SYMBOL_GPL(dw_pcie_link_set_max_speed);



void dw_pcie_link_set_n_fts(struct dw_pcie *pci, u32 n_fts)

{

	u32 val;



	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);

	val &= ~PORT_LOGIC_N_FTS_MASK;

	val |= n_fts & PORT_LOGIC_N_FTS_MASK;

	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);

}

EXPORT_SYMBOL_GPL(dw_pcie_link_set_n_fts);



static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)

{

	u32 val;

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