drm/amd/powerplay: use smu7 hwmgr to manager polaris10/11 (4be051ae) · Commits · 戴 / test

drivers/gpu/drm/amd/powerplay/hwmgr/Makefile

+0 −2

Original line number	Diff line number	Diff line
		@@ -9,8 +9,6 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
		tonga_hwmgr.o pppcielanes.o tonga_thermal.o\
		fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
		fiji_clockpowergating.o fiji_thermal.o \
		polaris10_hwmgr.o polaris10_powertune.o polaris10_thermal.o \
		polaris10_clockpowergating.o \
		smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
		smu7_clockpowergating.o iceland_hwmgr.o \
		iceland_clockpowergating.o iceland_thermal.o \

drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

+36 −2

Original line number	Diff line number	Diff line
		@@ -38,9 +38,9 @@
		extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
		extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
		extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr);
		extern int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);
		extern int iceland_hwmgr_init(struct pp_hwmgr *hwmgr);

		static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
		static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
		static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);

		@@ -89,7 +89,9 @@ int hwmgr_init(struct amd_pp_init pp_init, struct pp_instance handle)
		break;
		case CHIP_POLARIS11:
		case CHIP_POLARIS10:
		polaris10_hwmgr_init(hwmgr);
		smu7_hwmgr_init(hwmgr);
		polaris_set_asic_special_caps(hwmgr);
		hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
		break;
		default:
		return -EINVAL;
		@@ -206,6 +208,8 @@ int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
		}




		/**
		* Returns once the part of the register indicated by the mask has
		* reached the given value.The indirect space is described by giving
		@@ -710,3 +714,33 @@ int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
		return ret;
		}

		int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
		{
		/* power tune caps Assume disabled */
		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_SQRamping);
		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_DBRamping);
		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TDRamping);
		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TCPRamping);

		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_CAC);

		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_RegulatorHot);

		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_AutomaticDCTransition);

		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_TablelessHardwareInterface);

		if (hwmgr->chip_id == CHIP_POLARIS11)
		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_SPLLShutdownSupport);
		return 0;
		}

drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -709,6 +709,7 @@ extern int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
		extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
		extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);

		extern int smu7_hwmgr_init(struct pp_hwmgr *hwmgr);
		extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
		uint32_t sclk, uint16_t id, uint16_t *voltage);

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