Commit 34a564ea authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: implement fw image related smum interface for Polaris. 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 599a7e9f

drivers/gpu/drm/amd/powerplay/smumgr/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
# It provides the smu management services for the driver.



SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o \

	  polaris10_smumgr.o iceland_smumgr.o

	  polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o



AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))

drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c

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+2284 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.h

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+42 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2015 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef POLARIS10_SMC_H

#define POLARIS10_SMC_H



#include "smumgr.h"





int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);

int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr);

int polaris10_init_smc_table(struct pp_hwmgr *hwmgr);

int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);

int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr);

int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);

int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr);

uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member);

uint32_t polaris10_get_mac_definition(uint32_t value);

int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr);

bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr);



#endif

drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c

+21 −3
Original line number Diff line number Diff line
@@ -38,6 +38,8 @@ 
#include "ppatomctrl.h"

#include "pp_debug.h"

#include "cgs_common.h"

#include "polaris10_smc.h"

#include "smu7_ppsmc.h"



#define POLARIS10_SMC_SIZE 0x20000
@@ -46,7 +48,7 @@ 
#define MAX_STRING_SIZE             15

#define BUFFER_SIZETWO              131072  /* 128 *1024 */



#define SMC_RAM_END 0x40000

#define PPPOLARIS10_TARGETACTIVITY_DFLT                     50



static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {

	/*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
@@ -61,8 +63,8 @@ static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = { 
	{ 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }

};



static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 =

	{0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};

static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {

	0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};



/**

* Set the address for reading/writing the SMC SRAM space.
@@ -921,6 +923,8 @@ static int polaris10_smu_init(struct pp_smumgr *smumgr) 
	struct polaris10_smumgr *smu_data;

	uint8_t *internal_buf;

	uint64_t mc_addr = 0;

	int i;



	/* Allocate memory for backend private data */

	smu_data = (struct polaris10_smumgr *)(smumgr->backend);

	smu_data->header_buffer.data_size =
@@ -974,6 +978,9 @@ static int polaris10_smu_init(struct pp_smumgr *smumgr) 
	else

		smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;



	for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++)

		smu_data->activity_target[i] = PPPOLARIS10_TARGETACTIVITY_DFLT;



	return 0;

}
@@ -988,6 +995,17 @@ static const struct pp_smumgr_func polaris10_smu_funcs = { 
	.send_msg_to_smc_with_parameter = polaris10_send_msg_to_smc_with_parameter,

	.download_pptable_settings = NULL,

	.upload_pptable_settings = NULL,

	.update_smc_table = polaris10_update_smc_table,

	.get_offsetof = polaris10_get_offsetof,

	.process_firmware_header = polaris10_process_firmware_header,

	.init_smc_table = polaris10_init_smc_table,

	.update_sclk_threshold = polaris10_update_sclk_threshold,

	.thermal_avfs_enable = polaris10_thermal_avfs_enable,

	.thermal_setup_fan_table = polaris10_thermal_setup_fan_table,

	.populate_all_graphic_levels = polaris10_populate_all_graphic_levels,

	.populate_all_memory_levels = polaris10_populate_all_memory_levels,

	.get_mac_definition = polaris10_get_mac_definition,

	.is_dpm_running = polaris10_is_dpm_running,

};



int polaris10_smum_init(struct pp_smumgr *smumgr)

drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h

+19 −4
Original line number Diff line number Diff line
@@ -24,9 +24,13 @@ 
#ifndef _POLARIS10_SMUMANAGER_H

#define _POLARIS10_SMUMANAGER_H



#include <polaris10_ppsmc.h>



#include <pp_endian.h>

#include "smu74.h"

#include "smu74_discrete.h"





#define SMC_RAM_END 0x40000



struct polaris10_avfs {

	enum AVFS_BTC_STATUS avfs_btc_status;
@@ -65,7 +69,13 @@ struct polaris10_smumgr { 
	uint8_t *mec_image;

	struct polaris10_buffer_entry smu_buffer;

	struct polaris10_buffer_entry header_buffer;



	uint32_t                             soft_regs_start;

	uint32_t                             dpm_table_start;

	uint32_t                             mc_reg_table_start;

	uint32_t                             fan_table_start;

	uint32_t                             arb_table_start;



	uint8_t *read_rrm_straps;

	uint32_t read_drm_straps_mc_address_high;

	uint32_t read_drm_straps_mc_address_low;
@@ -74,15 +84,20 @@ struct polaris10_smumgr { 
	uint8_t protected_mode;

	uint8_t security_hard_key;

	struct polaris10_avfs  avfs;

	SMU74_Discrete_DpmTable              smc_state_table;

	struct SMU74_Discrete_Ulv            ulv_setting;

	struct SMU74_Discrete_PmFuses  power_tune_table;

	struct polaris10_range_table                range_table[NUM_SCLK_RANGE];

	const struct polaris10_pt_defaults       *power_tune_defaults;

	uint32_t                   activity_target[SMU74_MAX_LEVELS_GRAPHICS];

	uint32_t                   bif_sclk_table[SMU74_MAX_LEVELS_LINK];

};





int polaris10_smum_init(struct pp_smumgr *smumgr);



int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit);

int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit);

int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,

				const uint8_t *src, uint32_t byte_count, uint32_t limit);



#endif

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