Commit 4b0556a4 authored Mar 21, 2018 by Shawn Lin Committed by Heiko Stuebner Mar 23, 2018

clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228



commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase
if clock rate is zero") catches one gremlin again for clk-rk3228.c
that the parent of SDMMC phase clock should be sclk_sdmmc0, but not
sclk_sdmmc. However, the naming of the sdmmc clocks varies in the
manual with the card clock having the 0 while the hclk is named
without appended 0. So standardize one one format to prevent
confusion, as there also is only one (non-sdio) mmc controller on
the soc.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

parent 4ee3fd4a

drivers/clk/rockchip/clk-rk3228.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -387,7 +387,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
		RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
		RK2928_CLKGATE_CON(2), 15, GFLAGS),

		COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
		COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
		RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
		RK2928_CLKGATE_CON(2), 11, GFLAGS),

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