Commit 48a1b8d4 authored by Pankaj Bharadiya's avatar Pankaj Bharadiya Committed by Jani Nikula
Browse files

drm/i915: Make WARN* drm specific where drm_priv ptr is available 



drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.

Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_i915_private struct pointer is readily
available.

The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.

@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}

@rule2@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}

command: ls drivers/gpu/drm/i915/*.c | xargs spatch --sp-file \
			<script> --linux-spacing --in-place

Signed-off-by: default avatarPankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200115034455.17658-10-pankaj.laxminarayan.bharadiya@intel.com
parent 0d4c351a

drivers/gpu/drm/i915/i915_drv.c

+10 −9
Original line number Diff line number Diff line
@@ -1015,7 +1015,7 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv) 
		bxt_get_dimm_info(&dimm, val);

		type = bxt_get_dimm_type(val);



		WARN_ON(type != INTEL_DRAM_UNKNOWN &&

		drm_WARN_ON(&dev_priv->drm, type != INTEL_DRAM_UNKNOWN &&

			    dram_info->type != INTEL_DRAM_UNKNOWN &&

			    dram_info->type != type);
@@ -1805,7 +1805,7 @@ int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state) 
{

	int error;



	if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&

	if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&

			     state.event != PM_EVENT_FREEZE))

		return -EINVAL;
@@ -2429,7 +2429,8 @@ static int vlv_suspend_complete(struct drm_i915_private *dev_priv) 
	vlv_wait_for_gt_wells(dev_priv, false);



	mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;

	WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);

	drm_WARN_ON(&dev_priv->drm,

		    (I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);



	vlv_check_no_gt_access(dev_priv);
@@ -2495,7 +2496,7 @@ static int intel_runtime_suspend(struct device *kdev) 
	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;

	int ret = 0;



	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))

	if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))

		return -ENODEV;



	DRM_DEBUG_KMS("Suspending device\n");
@@ -2580,12 +2581,12 @@ static int intel_runtime_resume(struct device *kdev) 
	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;

	int ret = 0;



	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))

	if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))

		return -ENODEV;



	DRM_DEBUG_KMS("Resuming device\n");



	WARN_ON_ONCE(atomic_read(&rpm->wakeref_count));

	drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));

	disable_rpm_wakeref_asserts(rpm);



	intel_opregion_notify_adapter(dev_priv, PCI_D0);

drivers/gpu/drm/i915/i915_gem.c

+4 −3
Original line number Diff line number Diff line
@@ -1198,7 +1198,7 @@ void i915_gem_driver_release(struct drm_i915_private *dev_priv) 


	i915_gem_drain_freed_objects(dev_priv);



	WARN_ON(!list_empty(&dev_priv->gem.contexts.list));

	drm_WARN_ON(&dev_priv->drm, !list_empty(&dev_priv->gem.contexts.list));

}



static void i915_gem_init__mm(struct drm_i915_private *i915)
@@ -1226,7 +1226,7 @@ void i915_gem_cleanup_early(struct drm_i915_private *dev_priv) 
	i915_gem_drain_freed_objects(dev_priv);

	GEM_BUG_ON(!llist_empty(&dev_priv->mm.free_list));

	GEM_BUG_ON(atomic_read(&dev_priv->mm.free_count));

	WARN_ON(dev_priv->mm.shrink_count);

	drm_WARN_ON(&dev_priv->drm, dev_priv->mm.shrink_count);

}



int i915_gem_freeze(struct drm_i915_private *dev_priv)
@@ -1266,7 +1266,8 @@ int i915_gem_freeze_late(struct drm_i915_private *i915) 


	list_for_each_entry(obj, &i915->mm.shrink_list, mm.link) {

		i915_gem_object_lock(obj);

		WARN_ON(i915_gem_object_set_to_cpu_domain(obj, true));

		drm_WARN_ON(&i915->drm,

			    i915_gem_object_set_to_cpu_domain(obj, true));

		i915_gem_object_unlock(obj);

	}

drivers/gpu/drm/i915/i915_irq.c

+40 −35
Original line number Diff line number Diff line
@@ -262,7 +262,7 @@ i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, 
	u32 val;



	lockdep_assert_held(&dev_priv->irq_lock);

	WARN_ON(bits & ~mask);

	drm_WARN_ON(&dev_priv->drm, bits & ~mask);



	val = I915_READ(PORT_HOTPLUG_EN);

	val &= ~mask;
@@ -305,9 +305,9 @@ void ilk_update_display_irq(struct drm_i915_private *dev_priv, 


	lockdep_assert_held(&dev_priv->irq_lock);



	WARN_ON(enabled_irq_mask & ~interrupt_mask);

	drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);



	if (WARN_ON(!intel_irqs_enabled(dev_priv)))

	if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))

		return;



	new_val = dev_priv->irq_mask;
@@ -336,9 +336,9 @@ static void bdw_update_port_irq(struct drm_i915_private *dev_priv, 


	lockdep_assert_held(&dev_priv->irq_lock);



	WARN_ON(enabled_irq_mask & ~interrupt_mask);

	drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);



	if (WARN_ON(!intel_irqs_enabled(dev_priv)))

	if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))

		return;



	old_val = I915_READ(GEN8_DE_PORT_IMR);
@@ -369,9 +369,9 @@ void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, 


	lockdep_assert_held(&dev_priv->irq_lock);



	WARN_ON(enabled_irq_mask & ~interrupt_mask);

	drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);



	if (WARN_ON(!intel_irqs_enabled(dev_priv)))

	if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))

		return;



	new_val = dev_priv->de_irq_mask[pipe];
@@ -399,11 +399,11 @@ void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 
	sdeimr &= ~interrupt_mask;

	sdeimr |= (~enabled_irq_mask & interrupt_mask);



	WARN_ON(enabled_irq_mask & ~interrupt_mask);

	drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);



	lockdep_assert_held(&dev_priv->irq_lock);



	if (WARN_ON(!intel_irqs_enabled(dev_priv)))

	if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))

		return;



	I915_WRITE(SDEIMR, sdeimr);
@@ -425,13 +425,15 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, 
	 * On pipe A we don't support the PSR interrupt yet,

	 * on pipe B and C the same bit MBZ.

	 */

	if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))

	if (drm_WARN_ON_ONCE(&dev_priv->drm,

			     status_mask & PIPE_A_PSR_STATUS_VLV))

		return 0;

	/*

	 * On pipe B and C we don't support the PSR interrupt yet, on pipe

	 * A the same bit is for perf counters which we don't use either.

	 */

	if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))

	if (drm_WARN_ON_ONCE(&dev_priv->drm,

			     status_mask & PIPE_B_PSR_STATUS_VLV))

		return 0;



	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
@@ -443,7 +445,8 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, 
		enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;



out:

	WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||

	drm_WARN_ONCE(&dev_priv->drm,

		      enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||

		      status_mask & ~PIPESTAT_INT_STATUS_MASK,

		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",

		      pipe_name(pipe), enable_mask, status_mask);
@@ -457,12 +460,12 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv, 
	i915_reg_t reg = PIPESTAT(pipe);

	u32 enable_mask;



	WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,

	drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,

		      "pipe %c: status_mask=0x%x\n",

		      pipe_name(pipe), status_mask);



	lockdep_assert_held(&dev_priv->irq_lock);

	WARN_ON(!intel_irqs_enabled(dev_priv));

	drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));



	if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)

		return;
@@ -480,12 +483,12 @@ void i915_disable_pipestat(struct drm_i915_private *dev_priv, 
	i915_reg_t reg = PIPESTAT(pipe);

	u32 enable_mask;



	WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,

	drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,

		      "pipe %c: status_mask=0x%x\n",

		      pipe_name(pipe), status_mask);



	lockdep_assert_held(&dev_priv->irq_lock);

	WARN_ON(!intel_irqs_enabled(dev_priv));

	drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));



	if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)

		return;
@@ -777,7 +780,7 @@ bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int index, 
		IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) ||

		mode->private_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;



	if (WARN_ON(!mode->crtc_clock)) {

	if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {

		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "

				 "pipe %c\n", pipe_name(pipe));

		return false;
@@ -918,7 +921,7 @@ static void ivb_parity_work(struct work_struct *work) 
	mutex_lock(&dev_priv->drm.struct_mutex);



	/* If we've screwed up tracking, just let the interrupt fire again */

	if (WARN_ON(!dev_priv->l3_parity.which_slice))

	if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))

		goto out;



	misccpctl = I915_READ(GEN7_MISCCPCTL);
@@ -929,7 +932,8 @@ static void ivb_parity_work(struct work_struct *work) 
		i915_reg_t reg;



		slice--;

		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))

		if (drm_WARN_ON_ONCE(&dev_priv->drm,

				     slice >= NUM_L3_SLICES(dev_priv)))

			break;



		dev_priv->l3_parity.which_slice &= ~(1<<slice);
@@ -966,7 +970,7 @@ static void ivb_parity_work(struct work_struct *work) 
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);



out:

	WARN_ON(dev_priv->l3_parity.which_slice);

	drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);

	spin_lock_irq(&gt->irq_lock);

	gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));

	spin_unlock_irq(&gt->irq_lock);
@@ -1463,7 +1467,7 @@ static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) 
		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);

	}



	WARN_ONCE(1,

	drm_WARN_ONCE(&dev_priv->drm, 1,

		      "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",

		      I915_READ(PORT_HOTPLUG_STAT));
@@ -1844,8 +1848,9 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 
		tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;

		pins = hpd_icp;

	} else {

		WARN(!HAS_PCH_ICP(dev_priv),

		     "Unrecognized PCH type 0x%x\n", INTEL_PCH_TYPE(dev_priv));

		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),

			 "Unrecognized PCH type 0x%x\n",

			 INTEL_PCH_TYPE(dev_priv));



		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;

		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
@@ -2686,7 +2691,7 @@ static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv) 
	if (HAS_PCH_NOP(dev_priv))

		return;



	WARN_ON(I915_READ(SDEIER) != 0);

	drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);

	I915_WRITE(SDEIER, 0xffffffff);

	POSTING_READ(SDEIER);

}
@@ -2733,7 +2738,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) 
		enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |

			I915_LPE_PIPE_C_INTERRUPT;



	WARN_ON(dev_priv->irq_mask != ~0u);

	drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);



	dev_priv->irq_mask = ~enable_mask;
@@ -3418,7 +3423,7 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv) 
{

	u32 mask = SDE_GMBUS_ICP;



	WARN_ON(I915_READ(SDEIER) != 0);

	drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);

	I915_WRITE(SDEIER, 0xffffffff);

	POSTING_READ(SDEIER);

drivers/gpu/drm/i915/i915_pmu.c

+3 −3
Original line number Diff line number Diff line
@@ -448,7 +448,7 @@ static void engine_event_destroy(struct perf_event *event) 
	engine = intel_engine_lookup_user(i915,

					  engine_event_class(event),

					  engine_event_instance(event));

	if (WARN_ON_ONCE(!engine))

	if (drm_WARN_ON_ONCE(&i915->drm, !engine))

		return;



	if (engine_event_sample(event) == I915_SAMPLE_BUSY &&
@@ -584,7 +584,7 @@ static u64 __i915_pmu_event_read(struct perf_event *event) 
						  engine_event_class(event),

						  engine_event_instance(event));



		if (WARN_ON_ONCE(!engine)) {

		if (drm_WARN_ON_ONCE(&i915->drm, !engine)) {

			/* Do nothing */

		} else if (sample == I915_SAMPLE_BUSY &&

			   intel_engine_supports_stats(engine)) {
@@ -1186,7 +1186,7 @@ void i915_pmu_unregister(struct drm_i915_private *i915) 
	if (!pmu->base.event_init)

		return;



	WARN_ON(pmu->enable);

	drm_WARN_ON(&i915->drm, pmu->enable);



	hrtimer_cancel(&pmu->timer);

drivers/gpu/drm/i915/intel_csr.c

+2 −2
Original line number Diff line number Diff line
@@ -609,7 +609,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv, 


static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)

{

	WARN_ON(dev_priv->csr.wakeref);

	drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);

	dev_priv->csr.wakeref =

		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);

}
@@ -787,7 +787,7 @@ void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) 
		return;



	intel_csr_ucode_suspend(dev_priv);

	WARN_ON(dev_priv->csr.wakeref);

	drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);



	kfree(dev_priv->csr.dmc_payload);

}

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