Commit 47c9e0ce authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-rpi-cpufreq', 'clk-tegra', 'clk-simplify-provider.h',... 

Merge branches 'clk-rpi-cpufreq', 'clk-tegra', 'clk-simplify-provider.h', 'clk-sprd' and 'clk-at91' into clk-next

 - Support for CPU clks on Raspberry Pi devices
 - Slow clk support for AT91 SAM9X60 SoCs

* clk-rpi-cpufreq:
  clk: raspberrypi: register platform device for raspberrypi-cpufreq
  firmware: raspberrypi: register clk device
  clk: bcm283x: add driver interfacing with Raspberry Pi's firmware
  clk: bcm2835: remove pllb

* clk-tegra:
  clk: tegra: Do not enable PLL_RE_VCO on Tegra210
  clk: tegra: Warn if an enabled PLL is in IDDQ
  clk: tegra: Do not warn unnecessarily
  clk: tegra210: fix PLLU and PLLU_OUT1

* clk-simplify-provider.h:
  clk: consoldiate the __clk_get_hw() declarations
  clk: Unexport __clk_of_table
  clk: Remove ifdef for COMMON_CLK in clk-provider.h

* clk-sprd:
  clk: sprd: Add check for return value of sprd_clk_regmap_init()
  clk: sprd: Check error only for devm_regmap_init_mmio()
  clk: sprd: Switch from of_iomap() to devm_ioremap_resource()

* clk-at91:
  clk: at91: sckc: use dedicated functions to unregister clock
  clk: at91: sckc: improve error path for sama5d4 sck registration
  clk: at91: sckc: remove unnecessary line
  clk: at91: sckc: improve error path for sam9x5 sck register
  clk: at91: sckc: add support to free slow clock osclillator
  clk: at91: sckc: add support to free slow rc oscillator
  clk: at91: sckc: add support to free slow oscillator
  clk: at91: sckc: add support for SAM9X60
  dt-bindings: clk: at91: add bindings for SAM9X60's slow clock controller
  clk: at91: sckc: add support to specify registers bit offsets
  clk: at91: sckc: sama5d4 has no bypass support
parents a993be37 e2bb1834 e3527dca 1df37992 c974c48d ecbcc2aa

Documentation/devicetree/bindings/clock/at91-clock.txt

+4 −3
Original line number Diff line number Diff line
@@ -9,10 +9,11 @@ Slow Clock controller: 
Required properties:

- compatible : shall be one of the following:

	"atmel,at91sam9x5-sckc",

	"atmel,sama5d3-sckc" or

	"atmel,sama5d4-sckc":

	"atmel,sama5d3-sckc",

	"atmel,sama5d4-sckc" or

	"microchip,sam9x60-sckc":

		at91 SCKC (Slow Clock Controller)

- #clock-cells : shall be 0.

- #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0.

- clocks : shall be the input parent clock phandle for the clock.



Optional properties:

drivers/clk/at91/sckc.c

+214 −67
Original line number Diff line number Diff line
@@ -23,14 +23,18 @@ 
				 SLOW_CLOCK_FREQ)



#define	AT91_SCKC_CR			0x00

#define		AT91_SCKC_RCEN		(1 << 0)

#define		AT91_SCKC_OSC32EN	(1 << 1)

#define		AT91_SCKC_OSC32BYP	(1 << 2)

#define		AT91_SCKC_OSCSEL	(1 << 3)



struct clk_slow_bits {

	u32 cr_rcen;

	u32 cr_osc32en;

	u32 cr_osc32byp;

	u32 cr_oscsel;

};



struct clk_slow_osc {

	struct clk_hw hw;

	void __iomem *sckcr;

	const struct clk_slow_bits *bits;

	unsigned long startup_usec;

};
@@ -39,6 +43,7 @@ struct clk_slow_osc { 
struct clk_sama5d4_slow_osc {

	struct clk_hw hw;

	void __iomem *sckcr;

	const struct clk_slow_bits *bits;

	unsigned long startup_usec;

	bool prepared;

};
@@ -48,6 +53,7 @@ struct clk_sama5d4_slow_osc { 
struct clk_slow_rc_osc {

	struct clk_hw hw;

	void __iomem *sckcr;

	const struct clk_slow_bits *bits;

	unsigned long frequency;

	unsigned long accuracy;

	unsigned long startup_usec;
@@ -58,6 +64,7 @@ struct clk_slow_rc_osc { 
struct clk_sam9x5_slow {

	struct clk_hw hw;

	void __iomem *sckcr;

	const struct clk_slow_bits *bits;

	u8 parent;

};
@@ -69,10 +76,10 @@ static int clk_slow_osc_prepare(struct clk_hw *hw) 
	void __iomem *sckcr = osc->sckcr;

	u32 tmp = readl(sckcr);



	if (tmp & (AT91_SCKC_OSC32BYP | AT91_SCKC_OSC32EN))

	if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en))

		return 0;



	writel(tmp | AT91_SCKC_OSC32EN, sckcr);

	writel(tmp | osc->bits->cr_osc32en, sckcr);



	usleep_range(osc->startup_usec, osc->startup_usec + 1);
@@ -85,10 +92,10 @@ static void clk_slow_osc_unprepare(struct clk_hw *hw) 
	void __iomem *sckcr = osc->sckcr;

	u32 tmp = readl(sckcr);



	if (tmp & AT91_SCKC_OSC32BYP)

	if (tmp & osc->bits->cr_osc32byp)

		return;



	writel(tmp & ~AT91_SCKC_OSC32EN, sckcr);

	writel(tmp & ~osc->bits->cr_osc32en, sckcr);

}



static int clk_slow_osc_is_prepared(struct clk_hw *hw)
@@ -97,10 +104,10 @@ static int clk_slow_osc_is_prepared(struct clk_hw *hw) 
	void __iomem *sckcr = osc->sckcr;

	u32 tmp = readl(sckcr);



	if (tmp & AT91_SCKC_OSC32BYP)

	if (tmp & osc->bits->cr_osc32byp)

		return 1;



	return !!(tmp & AT91_SCKC_OSC32EN);

	return !!(tmp & osc->bits->cr_osc32en);

}



static const struct clk_ops slow_osc_ops = {
@@ -114,7 +121,8 @@ at91_clk_register_slow_osc(void __iomem *sckcr, 
			   const char *name,

			   const char *parent_name,

			   unsigned long startup,

			   bool bypass)

			   bool bypass,

			   const struct clk_slow_bits *bits)

{

	struct clk_slow_osc *osc;

	struct clk_hw *hw;
@@ -137,10 +145,11 @@ at91_clk_register_slow_osc(void __iomem *sckcr, 
	osc->hw.init = &init;

	osc->sckcr = sckcr;

	osc->startup_usec = startup;

	osc->bits = bits;



	if (bypass)

		writel((readl(sckcr) & ~AT91_SCKC_OSC32EN) | AT91_SCKC_OSC32BYP,

		       sckcr);

		writel((readl(sckcr) & ~osc->bits->cr_osc32en) |

					osc->bits->cr_osc32byp, sckcr);



	hw = &osc->hw;

	ret = clk_hw_register(NULL, &osc->hw);
@@ -152,6 +161,14 @@ at91_clk_register_slow_osc(void __iomem *sckcr, 
	return hw;

}



static void at91_clk_unregister_slow_osc(struct clk_hw *hw)

{

	struct clk_slow_osc *osc = to_clk_slow_osc(hw);



	clk_hw_unregister(hw);

	kfree(osc);

}



static unsigned long clk_slow_rc_osc_recalc_rate(struct clk_hw *hw,

						 unsigned long parent_rate)

{
@@ -173,7 +190,7 @@ static int clk_slow_rc_osc_prepare(struct clk_hw *hw) 
	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);

	void __iomem *sckcr = osc->sckcr;



	writel(readl(sckcr) | AT91_SCKC_RCEN, sckcr);

	writel(readl(sckcr) | osc->bits->cr_rcen, sckcr);



	usleep_range(osc->startup_usec, osc->startup_usec + 1);
@@ -185,14 +202,14 @@ static void clk_slow_rc_osc_unprepare(struct clk_hw *hw) 
	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);

	void __iomem *sckcr = osc->sckcr;



	writel(readl(sckcr) & ~AT91_SCKC_RCEN, sckcr);

	writel(readl(sckcr) & ~osc->bits->cr_rcen, sckcr);

}



static int clk_slow_rc_osc_is_prepared(struct clk_hw *hw)

{

	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);



	return !!(readl(osc->sckcr) & AT91_SCKC_RCEN);

	return !!(readl(osc->sckcr) & osc->bits->cr_rcen);

}



static const struct clk_ops slow_rc_osc_ops = {
@@ -208,7 +225,8 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, 
			      const char *name,

			      unsigned long frequency,

			      unsigned long accuracy,

			      unsigned long startup)

			      unsigned long startup,

			      const struct clk_slow_bits *bits)

{

	struct clk_slow_rc_osc *osc;

	struct clk_hw *hw;
@@ -230,6 +248,7 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, 


	osc->hw.init = &init;

	osc->sckcr = sckcr;

	osc->bits = bits;

	osc->frequency = frequency;

	osc->accuracy = accuracy;

	osc->startup_usec = startup;
@@ -244,6 +263,14 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr, 
	return hw;

}



static void at91_clk_unregister_slow_rc_osc(struct clk_hw *hw)

{

	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);



	clk_hw_unregister(hw);

	kfree(osc);

}



static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index)

{

	struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
@@ -255,14 +282,14 @@ static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index) 


	tmp = readl(sckcr);



	if ((!index && !(tmp & AT91_SCKC_OSCSEL)) ||

	    (index && (tmp & AT91_SCKC_OSCSEL)))

	if ((!index && !(tmp & slowck->bits->cr_oscsel)) ||

	    (index && (tmp & slowck->bits->cr_oscsel)))

		return 0;



	if (index)

		tmp |= AT91_SCKC_OSCSEL;

		tmp |= slowck->bits->cr_oscsel;

	else

		tmp &= ~AT91_SCKC_OSCSEL;

		tmp &= ~slowck->bits->cr_oscsel;



	writel(tmp, sckcr);
@@ -275,7 +302,7 @@ static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw) 
{

	struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);



	return !!(readl(slowck->sckcr) & AT91_SCKC_OSCSEL);

	return !!(readl(slowck->sckcr) & slowck->bits->cr_oscsel);

}



static const struct clk_ops sam9x5_slow_ops = {
@@ -287,7 +314,8 @@ static struct clk_hw * __init 
at91_clk_register_sam9x5_slow(void __iomem *sckcr,

			      const char *name,

			      const char **parent_names,

			      int num_parents)

			      int num_parents,

			      const struct clk_slow_bits *bits)

{

	struct clk_sam9x5_slow *slowck;

	struct clk_hw *hw;
@@ -309,7 +337,8 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr, 


	slowck->hw.init = &init;

	slowck->sckcr = sckcr;

	slowck->parent = !!(readl(sckcr) & AT91_SCKC_OSCSEL);

	slowck->bits = bits;

	slowck->parent = !!(readl(sckcr) & slowck->bits->cr_oscsel);



	hw = &slowck->hw;

	ret = clk_hw_register(NULL, &slowck->hw);
@@ -321,22 +350,33 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr, 
	return hw;

}



static void at91_clk_unregister_sam9x5_slow(struct clk_hw *hw)

{

	struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);



	clk_hw_unregister(hw);

	kfree(slowck);

}



static void __init at91sam9x5_sckc_register(struct device_node *np,

					    unsigned int rc_osc_startup_us)

					    unsigned int rc_osc_startup_us,

					    const struct clk_slow_bits *bits)

{

	const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };

	void __iomem *regbase = of_iomap(np, 0);

	struct device_node *child = NULL;

	const char *xtal_name;

	struct clk_hw *hw;

	struct clk_hw *slow_rc, *slow_osc, *slowck;

	bool bypass;

	int ret;



	if (!regbase)

		return;



	hw = at91_clk_register_slow_rc_osc(regbase, parent_names[0], 32768,

					   50000000, rc_osc_startup_us);

	if (IS_ERR(hw))

	slow_rc = at91_clk_register_slow_rc_osc(regbase, parent_names[0],

						32768, 50000000,

						rc_osc_startup_us, bits);

	if (IS_ERR(slow_rc))

		return;



	xtal_name = of_clk_get_parent_name(np, 0);
@@ -344,7 +384,7 @@ static void __init at91sam9x5_sckc_register(struct device_node *np, 
		/* DT backward compatibility */

		child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow-osc");

		if (!child)

			return;

			goto unregister_slow_rc;



		xtal_name = of_clk_get_parent_name(child, 0);

		bypass = of_property_read_bool(child, "atmel,osc-bypass");
@@ -355,38 +395,133 @@ static void __init at91sam9x5_sckc_register(struct device_node *np, 
	}



	if (!xtal_name)

		return;

		goto unregister_slow_rc;



	hw = at91_clk_register_slow_osc(regbase, parent_names[1], xtal_name,

					1200000, bypass);

	if (IS_ERR(hw))

		return;

	slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],

					      xtal_name, 1200000, bypass, bits);

	if (IS_ERR(slow_osc))

		goto unregister_slow_rc;



	hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2);

	if (IS_ERR(hw))

		return;



	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);

	slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names,

					       2, bits);

	if (IS_ERR(slowck))

		goto unregister_slow_osc;



	/* DT backward compatibility */

	if (child)

		of_clk_add_hw_provider(child, of_clk_hw_simple_get, hw);

		ret = of_clk_add_hw_provider(child, of_clk_hw_simple_get,

					     slowck);

	else

		ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, slowck);



	if (WARN_ON(ret))

		goto unregister_slowck;



	return;



unregister_slowck:

	at91_clk_unregister_sam9x5_slow(slowck);

unregister_slow_osc:

	at91_clk_unregister_slow_osc(slow_osc);

unregister_slow_rc:

	at91_clk_unregister_slow_rc_osc(slow_rc);

}



static const struct clk_slow_bits at91sam9x5_bits = {

	.cr_rcen = BIT(0),

	.cr_osc32en = BIT(1),

	.cr_osc32byp = BIT(2),

	.cr_oscsel = BIT(3),

};



static void __init of_at91sam9x5_sckc_setup(struct device_node *np)

{

	at91sam9x5_sckc_register(np, 75);

	at91sam9x5_sckc_register(np, 75, &at91sam9x5_bits);

}

CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",

	       of_at91sam9x5_sckc_setup);



static void __init of_sama5d3_sckc_setup(struct device_node *np)

{

	at91sam9x5_sckc_register(np, 500);

	at91sam9x5_sckc_register(np, 500, &at91sam9x5_bits);

}

CLK_OF_DECLARE(sama5d3_clk_sckc, "atmel,sama5d3-sckc",

	       of_sama5d3_sckc_setup);



static const struct clk_slow_bits at91sam9x60_bits = {

	.cr_osc32en = BIT(1),

	.cr_osc32byp = BIT(2),

	.cr_oscsel = BIT(24),

};



static void __init of_sam9x60_sckc_setup(struct device_node *np)

{

	void __iomem *regbase = of_iomap(np, 0);

	struct clk_hw_onecell_data *clk_data;

	struct clk_hw *slow_rc, *slow_osc;

	const char *xtal_name;

	const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };

	bool bypass;

	int ret;



	if (!regbase)

		return;



	slow_rc = clk_hw_register_fixed_rate(NULL, parent_names[0], NULL, 0,

					     32768);

	if (IS_ERR(slow_rc))

		return;



	xtal_name = of_clk_get_parent_name(np, 0);

	if (!xtal_name)

		goto unregister_slow_rc;



	bypass = of_property_read_bool(np, "atmel,osc-bypass");

	slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],

					      xtal_name, 5000000, bypass,

					      &at91sam9x60_bits);

	if (IS_ERR(slow_osc))

		goto unregister_slow_rc;



	clk_data = kzalloc(sizeof(*clk_data) + (2 * sizeof(struct clk_hw *)),

			   GFP_KERNEL);

	if (!clk_data)

		goto unregister_slow_osc;



	/* MD_SLCK and TD_SLCK. */

	clk_data->num = 2;

	clk_data->hws[0] = clk_hw_register_fixed_rate(NULL, "md_slck",

						      parent_names[0],

						      0, 32768);

	if (IS_ERR(clk_data->hws[0]))

		goto clk_data_free;



	clk_data->hws[1] = at91_clk_register_sam9x5_slow(regbase, "td_slck",

							 parent_names, 2,

							 &at91sam9x60_bits);

	if (IS_ERR(clk_data->hws[1]))

		goto unregister_md_slck;



	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);

	if (WARN_ON(ret))

		goto unregister_td_slck;



	return;



unregister_td_slck:

	at91_clk_unregister_sam9x5_slow(clk_data->hws[1]);

unregister_md_slck:

	clk_hw_unregister(clk_data->hws[0]);

clk_data_free:

	kfree(clk_data);

unregister_slow_osc:

	at91_clk_unregister_slow_osc(slow_osc);

unregister_slow_rc:

	clk_hw_unregister(slow_rc);

}

CLK_OF_DECLARE(sam9x60_clk_sckc, "microchip,sam9x60-sckc",

	       of_sam9x60_sckc_setup);



static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw)

{

	struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw);
@@ -398,7 +533,7 @@ static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw) 
	 * Assume that if it has already been selected (for example by the

	 * bootloader), enough time has aready passed.

	 */

	if ((readl(osc->sckcr) & AT91_SCKC_OSCSEL)) {

	if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) {

		osc->prepared = true;

		return 0;

	}
@@ -421,33 +556,35 @@ static const struct clk_ops sama5d4_slow_osc_ops = { 
	.is_prepared = clk_sama5d4_slow_osc_is_prepared,

};



static const struct clk_slow_bits at91sama5d4_bits = {

	.cr_oscsel = BIT(3),

};



static void __init of_sama5d4_sckc_setup(struct device_node *np)

{

	void __iomem *regbase = of_iomap(np, 0);

	struct clk_hw *hw;

	struct clk_hw *slow_rc, *slowck;

	struct clk_sama5d4_slow_osc *osc;

	struct clk_init_data init;

	const char *xtal_name;

	const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };

	bool bypass;

	int ret;



	if (!regbase)

		return;



	hw = clk_hw_register_fixed_rate_with_accuracy(NULL, parent_names[0],

	slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL,

							   parent_names[0],

							   NULL, 0, 32768,

							   250000000);

	if (IS_ERR(hw))

	if (IS_ERR(slow_rc))

		return;



	xtal_name = of_clk_get_parent_name(np, 0);



	bypass = of_property_read_bool(np, "atmel,osc-bypass");



	osc = kzalloc(sizeof(*osc), GFP_KERNEL);

	if (!osc)

		return;

		goto unregister_slow_rc;



	init.name = parent_names[1];

	init.ops = &sama5d4_slow_osc_ops;
@@ -458,22 +595,32 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np) 
	osc->hw.init = &init;

	osc->sckcr = regbase;

	osc->startup_usec = 1200000;

	osc->bits = &at91sama5d4_bits;



	if (bypass)

		writel((readl(regbase) | AT91_SCKC_OSC32BYP), regbase);



	hw = &osc->hw;

	ret = clk_hw_register(NULL, &osc->hw);

	if (ret) {

		kfree(osc);

		return;

	}

	if (ret)

		goto free_slow_osc_data;



	slowck = at91_clk_register_sam9x5_slow(regbase, "slowck",

					       parent_names, 2,

					       &at91sama5d4_bits);

	if (IS_ERR(slowck))

		goto unregister_slow_osc;



	ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, slowck);

	if (WARN_ON(ret))

		goto unregister_slowck;



	hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2);

	if (IS_ERR(hw))

	return;



	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);

unregister_slowck:

	at91_clk_unregister_sam9x5_slow(slowck);

unregister_slow_osc:

	clk_hw_unregister(&osc->hw);

free_slow_osc_data:

	kfree(osc);

unregister_slow_rc:

	clk_hw_unregister(slow_rc);

}

CLK_OF_DECLARE(sama5d4_clk_sckc, "atmel,sama5d4-sckc",

	       of_sama5d4_sckc_setup);

drivers/clk/bcm/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -72,3 +72,10 @@ config CLK_BCM_SR 
	default ARCH_BCM_IPROC

	help

	  Enable common clock framework support for the Broadcom Stingray SoC



config CLK_RASPBERRYPI

	tristate "Raspberry Pi firmware based clock support"

	depends on RASPBERRYPI_FIRMWARE || (COMPILE_TEST && !RASPBERRYPI_FIRMWARE)

	help

	  Enable common clock framework support for Raspberry Pi's firmware

	  dependent clocks

drivers/clk/bcm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o 
obj-$(CONFIG_COMMON_CLK_IPROC)	+= clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o

obj-$(CONFIG_CLK_BCM2835)	+= clk-bcm2835.o

obj-$(CONFIG_CLK_BCM2835)	+= clk-bcm2835-aux.o

obj-$(CONFIG_CLK_RASPBERRYPI)	+= clk-raspberrypi.o

obj-$(CONFIG_ARCH_BCM_53573)	+= clk-bcm53573-ilp.o

obj-$(CONFIG_CLK_BCM_CYGNUS)	+= clk-cygnus.o

obj-$(CONFIG_CLK_BCM_HR2)	+= clk-hr2.o

drivers/clk/bcm/clk-bcm2835.c

+4 −24
Original line number Diff line number Diff line
@@ -1651,30 +1651,10 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { 
		.fixed_divider = 1,

		.flags = CLK_SET_RATE_PARENT),



	/* PLLB is used for the ARM's clock. */

	[BCM2835_PLLB]		= REGISTER_PLL(

		.name = "pllb",

		.cm_ctrl_reg = CM_PLLB,

		.a2w_ctrl_reg = A2W_PLLB_CTRL,

		.frac_reg = A2W_PLLB_FRAC,

		.ana_reg_base = A2W_PLLB_ANA0,

		.reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,

		.lock_mask = CM_LOCK_FLOCKB,



		.ana = &bcm2835_ana_default,



		.min_rate = 600000000u,

		.max_rate = 3000000000u,

		.max_fb_rate = BCM2835_MAX_FB_RATE),

	[BCM2835_PLLB_ARM]	= REGISTER_PLL_DIV(

		.name = "pllb_arm",

		.source_pll = "pllb",

		.cm_reg = CM_PLLB,

		.a2w_reg = A2W_PLLB_ARM,

		.load_mask = CM_PLLB_LOADARM,

		.hold_mask = CM_PLLB_HOLDARM,

		.fixed_divider = 1,

		.flags = CLK_SET_RATE_PARENT),

	/*

	 * PLLB is used for the ARM's clock. Controlled by firmware, see

	 * clk-raspberrypi.c.

	 */



	/*

	 * PLLC is the core PLL, used to drive the core VPU clock.

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