Commit a993be37 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-debugfs', 'clk-unused', 'clk-refactor' and 'clk-qoriq' into clk-next 

 - Add a 'clk_parent' file in clk debugfs
 - Remove dead code in various clk drivers

* clk-debugfs:
  clk: Add clk_parent entry in debugfs

* clk-unused:
  clk: qcom: Fix -Wunused-const-variable
  clk: mmp: frac: Remove set but not used variable 'prev_rate'
  clk: ti: Remove unused functions
  clk: mediatek: mt8516: Remove unused variable

* clk-refactor:
  clk: clk-cdce706: simplify getting the adapter of a client
  clk: Simplify clk_core_can_round()

* clk-qoriq:
  clk: qoriq: add support for lx2160a
parents dfe1d3a2 e5e89247 da642427 df095f99 78a5ba8f

drivers/clk/clk-cdce706.c

+1 −1
Original line number Diff line number Diff line
@@ -633,7 +633,7 @@ of_clk_cdce_get(struct of_phandle_args *clkspec, void *data) 
static int cdce706_probe(struct i2c_client *client,

			 const struct i2c_device_id *id)

{

	struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);

	struct i2c_adapter *adapter = client->adapter;

	struct cdce706_dev_data *cdce;

	int ret;

drivers/clk/clk-qoriq.c

+12 −0
Original line number Diff line number Diff line
@@ -637,6 +637,17 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		.pll_mask = 0x37,

		.flags = CG_VER3 | CG_LITTLE_ENDIAN,

	},

	{

		.compat = "fsl,lx2160a-clockgen",

		.cmux_groups = {

			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb

		},

		.cmux_to_group = {

			0, 0, 0, 0, 1, 1, 1, 1, -1

		},

		.pll_mask = 0x37,

		.flags = CG_VER3 | CG_LITTLE_ENDIAN,

	},

	{

		.compat = "fsl,p2041-clockgen",

		.guts_compat = "fsl,qoriq-device-config-1.0",
@@ -1496,6 +1507,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); 
CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);

drivers/clk/clk.c

+16 −4
Original line number Diff line number Diff line
@@ -1324,10 +1324,7 @@ static void clk_core_init_rate_req(struct clk_core * const core, 


static bool clk_core_can_round(struct clk_core * const core)

{

	if (core->ops->determine_rate || core->ops->round_rate)

		return true;



	return false;

	return core->ops->determine_rate || core->ops->round_rate;

}



static int clk_core_round_rate_nolock(struct clk_core *core,
@@ -3045,6 +3042,17 @@ static int possible_parents_show(struct seq_file *s, void *data) 
}

DEFINE_SHOW_ATTRIBUTE(possible_parents);



static int current_parent_show(struct seq_file *s, void *data)

{

	struct clk_core *core = s->private;



	if (core->parent)

		seq_printf(s, "%s\n", core->parent->name);



	return 0;

}

DEFINE_SHOW_ATTRIBUTE(current_parent);



static int clk_duty_cycle_show(struct seq_file *s, void *data)

{

	struct clk_core *core = s->private;
@@ -3077,6 +3085,10 @@ static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry) 
	debugfs_create_file("clk_duty_cycle", 0444, root, core,

			    &clk_duty_cycle_fops);



	if (core->num_parents > 0)

		debugfs_create_file("clk_parent", 0444, root, core,

				    &current_parent_fops);



	if (core->num_parents > 1)

		debugfs_create_file("clk_possible_parents", 0444, root, core,

				    &possible_parents_fops);

drivers/clk/mediatek/clk-mt8516.c

+0 −5
Original line number Diff line number Diff line
@@ -231,11 +231,6 @@ static const char * const nfi1x_pad_parents[] __initconst = { 
	"nfi1x_ck"

};



static const char * const ddrphycfg_parents[] __initconst = {

	"clk26m_ck",

	"mainpll_d16"

};



static const char * const usb_78m_parents[] __initconst = {

	"clk_null",

	"clk26m_ck",

drivers/clk/mmp/clk-frac.c

+1 −2
Original line number Diff line number Diff line
@@ -78,11 +78,10 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate, 
	struct mmp_clk_factor_masks *masks = factor->masks;

	int i;

	unsigned long val;

	unsigned long prev_rate, rate = 0;

	unsigned long rate = 0;

	unsigned long flags = 0;



	for (i = 0; i < factor->ftbl_cnt; i++) {

		prev_rate = rate;

		rate = (((prate / 10000) * factor->ftbl[i].den) /

			(factor->ftbl[i].num * factor->masks->factor)) * 10000;

		if (rate > drate)

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