Commit 477bfeb9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2020-05-01' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regular scheduled fixes for graphics. Nothing to extreme bunch of
  amdgpu fixes, i915 and qxl fixes, along with some misc ones.

  All seems to be progressing normally.

  core:
   - EDID off by one DTD fix
   - DP mst write return code fix

  dma-buf:
   - fix SET_NAME ioctl uapi
   - doc fixes

  amdgpu:
   - Fix a green screen on resume issue
   - PM fixes for SR-IOV SDMA fix for navi
   - Renoir display fixes
   - Cursor and pageflip stuttering fixes
   - Misc additional display fixes
   - (uapi) Add additional DCC tiling flags for navi1x

  i915:
   - Fix selftest refcnt leak (Xiyu)
   - Fix gem vma lock (Chris)
   - Fix gt's i915_request.timeline acquire by checking if cacheline is
     valid (Chris)
   - Fix IRQ postinistall fault masks (Matt)

  qxl:
   - use after gree fix
   - fix lost kunmap
   - release leak fix

  virtio:
   - context destruction fix"

* tag 'drm-fixes-2020-05-01' of git://anongit.freedesktop.org/drm/drm: (26 commits)
  dma-buf: fix documentation build warnings
  drm/qxl: qxl_release use after free
  drm/qxl: lost qxl_bo_kunmap_atomic_page in qxl_image_init_helper()
  drm/i915: Use proper fault mask in interrupt postinstall too
  drm/amd/display: Use cursor locking to prevent flip delays
  drm/amd/display: Update downspread percent to match spreadsheet for DCN2.1
  drm/amd/display: Defer cursor update around VUPDATE for all ASIC
  drm/amd/display: fix rn soc bb update
  drm/amd/display: check if REFCLK_CNTL register is present
  drm/amdgpu: bump version for invalidate L2 before SDMA IBs
  drm/amdgpu: invalidate L2 before SDMA IBs (v2)
  drm/amdgpu: add tiling flags from Mesa
  drm/amd/powerplay: avoid using pm_en before it is initialized revised
  Revert "drm/amd/powerplay: avoid using pm_en before it is initialized"
  drm/qxl: qxl_release leak in qxl_hw_surface_alloc()
  drm/qxl: qxl_release leak in qxl_draw_dirty_fb()
  drm/virtio: only destroy created contexts
  drm/dp_mst: Fix drm_dp_send_dpcd_write() return code
  drm/i915/gt: Check cacheline is valid before acquiring
  drm/i915/gem: Hold obj->vma.lock over for_each_ggtt_vma()
  ...
parents cebcff3a e3dcd86b

drivers/dma-buf/dma-buf.c

+4 −3
Original line number Diff line number Diff line
@@ -388,7 +388,8 @@ static long dma_buf_ioctl(struct file *file, 


		return ret;



	case DMA_BUF_SET_NAME:

	case DMA_BUF_SET_NAME_A:

	case DMA_BUF_SET_NAME_B:

		return dma_buf_set_name(dmabuf, (const char __user *)arg);



	default:
@@ -655,8 +656,8 @@ EXPORT_SYMBOL_GPL(dma_buf_put); 
 * calls attach() of dma_buf_ops to allow device-specific attach functionality

 * @dmabuf:		[in]	buffer to attach device to.

 * @dev:		[in]	device to be attached.

 * @importer_ops	[in]	importer operations for the attachment

 * @importer_priv	[in]	importer private pointer for the attachment

 * @importer_ops:	[in]	importer operations for the attachment

 * @importer_priv:	[in]	importer private pointer for the attachment

 *

 * Returns struct dma_buf_attachment pointer for this attachment. Attachments

 * must be cleaned up by calling dma_buf_detach().

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -85,9 +85,10 @@ 
 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches

 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask

 * - 3.36.0 - Allow reading more status registers on si/cik

 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness

 */

#define KMS_DRIVER_MAJOR	3

#define KMS_DRIVER_MINOR	36

#define KMS_DRIVER_MINOR	37

#define KMS_DRIVER_PATCHLEVEL	0



int amdgpu_vram_limit = 0;

drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h

+16 −0
Original line number Diff line number Diff line
@@ -73,6 +73,22 @@ 
#define SDMA_OP_AQL_COPY  0

#define SDMA_OP_AQL_BARRIER_OR  0



#define SDMA_GCR_RANGE_IS_PA		(1 << 18)

#define SDMA_GCR_SEQ(x)			(((x) & 0x3) << 16)

#define SDMA_GCR_GL2_WB			(1 << 15)

#define SDMA_GCR_GL2_INV		(1 << 14)

#define SDMA_GCR_GL2_DISCARD		(1 << 13)

#define SDMA_GCR_GL2_RANGE(x)		(((x) & 0x3) << 11)

#define SDMA_GCR_GL2_US			(1 << 10)

#define SDMA_GCR_GL1_INV		(1 << 9)

#define SDMA_GCR_GLV_INV		(1 << 8)

#define SDMA_GCR_GLK_INV		(1 << 7)

#define SDMA_GCR_GLK_WB			(1 << 6)

#define SDMA_GCR_GLM_INV		(1 << 5)

#define SDMA_GCR_GLM_WB			(1 << 4)

#define SDMA_GCR_GL1_RANGE(x)		(((x) & 0x3) << 2)

#define SDMA_GCR_GLI_INV(x)		(((x) & 0x3) << 0)



/*define for op field*/

#define SDMA_PKT_HEADER_op_offset 0

#define SDMA_PKT_HEADER_op_mask   0x000000FF

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

+13 −1
Original line number Diff line number Diff line
@@ -382,6 +382,18 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 
	unsigned vmid = AMDGPU_JOB_GET_VMID(job);

	uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);



	/* Invalidate L2, because if we don't do it, we might get stale cache

	 * lines from previous IBs.

	 */

	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));

	amdgpu_ring_write(ring, 0);

	amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |

				 SDMA_GCR_GL2_WB |

				 SDMA_GCR_GLM_INV |

				 SDMA_GCR_GLM_WB) << 16);

	amdgpu_ring_write(ring, 0xffffff80);

	amdgpu_ring_write(ring, 0xffff);



	/* An IB packet must end on a 8 DW boundary--the next dword

	 * must be on a 8-dword boundary. Our IB packet below is 6

	 * dwords long, thus add x number of NOPs, such that, in
@@ -1595,7 +1607,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +

		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +

		10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */

	.emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */

	.emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */

	.emit_ib = sdma_v5_0_ring_emit_ib,

	.emit_fence = sdma_v5_0_ring_emit_fence,

	.emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+29 −9
Original line number Diff line number Diff line
@@ -3340,7 +3340,8 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev, 
			  const union dc_tiling_info *tiling_info,

			  const uint64_t info,

			  struct dc_plane_dcc_param *dcc,

			  struct dc_plane_address *address)

			  struct dc_plane_address *address,

			  bool force_disable_dcc)

{

	struct dc *dc = adev->dm.dc;

	struct dc_dcc_surface_param input;
@@ -3352,6 +3353,9 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev, 
	memset(&input, 0, sizeof(input));

	memset(&output, 0, sizeof(output));



	if (force_disable_dcc)

		return 0;



	if (!offset)

		return 0;
@@ -3401,7 +3405,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, 
			     union dc_tiling_info *tiling_info,

			     struct plane_size *plane_size,

			     struct dc_plane_dcc_param *dcc,

			     struct dc_plane_address *address)

			     struct dc_plane_address *address,

			     bool force_disable_dcc)

{

	const struct drm_framebuffer *fb = &afb->base;

	int ret;
@@ -3507,7 +3512,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, 


		ret = fill_plane_dcc_attributes(adev, afb, format, rotation,

						plane_size, tiling_info,

						tiling_flags, dcc, address);

						tiling_flags, dcc, address,

						force_disable_dcc);

		if (ret)

			return ret;

	}
@@ -3599,7 +3605,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 
			    const struct drm_plane_state *plane_state,

			    const uint64_t tiling_flags,

			    struct dc_plane_info *plane_info,

			    struct dc_plane_address *address)

			    struct dc_plane_address *address,

			    bool force_disable_dcc)

{

	const struct drm_framebuffer *fb = plane_state->fb;

	const struct amdgpu_framebuffer *afb =
@@ -3681,7 +3688,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 
					   plane_info->rotation, tiling_flags,

					   &plane_info->tiling_info,

					   &plane_info->plane_size,

					   &plane_info->dcc, address);

					   &plane_info->dcc, address,

					   force_disable_dcc);

	if (ret)

		return ret;
@@ -3704,6 +3712,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, 
	struct dc_plane_info plane_info;

	uint64_t tiling_flags;

	int ret;

	bool force_disable_dcc = false;



	ret = fill_dc_scaling_info(plane_state, &scaling_info);

	if (ret)
@@ -3718,9 +3727,11 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, 
	if (ret)

		return ret;



	force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;

	ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,

					  &plane_info,

					  &dc_plane_state->address);

					  &dc_plane_state->address,

					  force_disable_dcc);

	if (ret)

		return ret;
@@ -5342,6 +5353,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 
	uint64_t tiling_flags;

	uint32_t domain;

	int r;

	bool force_disable_dcc = false;



	dm_plane_state_old = to_dm_plane_state(plane->state);

	dm_plane_state_new = to_dm_plane_state(new_state);
@@ -5400,11 +5412,13 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 
			dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {

		struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;



		force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;

		fill_plane_buffer_attributes(

			adev, afb, plane_state->format, plane_state->rotation,

			tiling_flags, &plane_state->tiling_info,

			&plane_state->plane_size, &plane_state->dcc,

			&plane_state->address);

			&plane_state->address,

			force_disable_dcc);

	}



	return 0;
@@ -6676,7 +6690,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 
		fill_dc_plane_info_and_addr(

			dm->adev, new_plane_state, tiling_flags,

			&bundle->plane_infos[planes_count],

			&bundle->flip_addrs[planes_count].address);

			&bundle->flip_addrs[planes_count].address,

			false);



		DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n",

				 new_plane_state->plane->index,

				 bundle->plane_infos[planes_count].dcc.enable);



		bundle->surface_updates[planes_count].plane_info =

			&bundle->plane_infos[planes_count];
@@ -8096,7 +8115,8 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm, 
				ret = fill_dc_plane_info_and_addr(

					dm->adev, new_plane_state, tiling_flags,

					plane_info,

					&flip_addr->address);

					&flip_addr->address,

					false);

				if (ret)

					goto cleanup;

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