Commit e3dcd86b authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.7-2020-04-29' of... 

Merge tag 'amd-drm-fixes-5.7-2020-04-29' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

amd-drm-fixes-5.7-2020-04-29:

amdgpu:
- Fix a green screen on resume issue
- PM fixes for SR-IOV
- SDMA fix for navi
- Renoir display fixes
- Cursor and pageflip stuttering fixes
- Misc additional display fixes

UAPI:
- Add additional DCC tiling flags for navi1x
  Used by: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697



Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200429212008.4306-1-alexander.deucher@amd.com
parents a979bb70 b2a7b0ce

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -85,9 +85,10 @@ 
 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches

 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask

 * - 3.36.0 - Allow reading more status registers on si/cik

 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness

 */

#define KMS_DRIVER_MAJOR	3

#define KMS_DRIVER_MINOR	36

#define KMS_DRIVER_MINOR	37

#define KMS_DRIVER_PATCHLEVEL	0



int amdgpu_vram_limit = 0;

drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h

+16 −0
Original line number Diff line number Diff line
@@ -73,6 +73,22 @@ 
#define SDMA_OP_AQL_COPY  0

#define SDMA_OP_AQL_BARRIER_OR  0



#define SDMA_GCR_RANGE_IS_PA		(1 << 18)

#define SDMA_GCR_SEQ(x)			(((x) & 0x3) << 16)

#define SDMA_GCR_GL2_WB			(1 << 15)

#define SDMA_GCR_GL2_INV		(1 << 14)

#define SDMA_GCR_GL2_DISCARD		(1 << 13)

#define SDMA_GCR_GL2_RANGE(x)		(((x) & 0x3) << 11)

#define SDMA_GCR_GL2_US			(1 << 10)

#define SDMA_GCR_GL1_INV		(1 << 9)

#define SDMA_GCR_GLV_INV		(1 << 8)

#define SDMA_GCR_GLK_INV		(1 << 7)

#define SDMA_GCR_GLK_WB			(1 << 6)

#define SDMA_GCR_GLM_INV		(1 << 5)

#define SDMA_GCR_GLM_WB			(1 << 4)

#define SDMA_GCR_GL1_RANGE(x)		(((x) & 0x3) << 2)

#define SDMA_GCR_GLI_INV(x)		(((x) & 0x3) << 0)



/*define for op field*/

#define SDMA_PKT_HEADER_op_offset 0

#define SDMA_PKT_HEADER_op_mask   0x000000FF

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

+13 −1
Original line number Diff line number Diff line
@@ -382,6 +382,18 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 
	unsigned vmid = AMDGPU_JOB_GET_VMID(job);

	uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);



	/* Invalidate L2, because if we don't do it, we might get stale cache

	 * lines from previous IBs.

	 */

	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));

	amdgpu_ring_write(ring, 0);

	amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV |

				 SDMA_GCR_GL2_WB |

				 SDMA_GCR_GLM_INV |

				 SDMA_GCR_GLM_WB) << 16);

	amdgpu_ring_write(ring, 0xffffff80);

	amdgpu_ring_write(ring, 0xffff);



	/* An IB packet must end on a 8 DW boundary--the next dword

	 * must be on a 8-dword boundary. Our IB packet below is 6

	 * dwords long, thus add x number of NOPs, such that, in
@@ -1595,7 +1607,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +

		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +

		10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */

	.emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */

	.emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */

	.emit_ib = sdma_v5_0_ring_emit_ib,

	.emit_fence = sdma_v5_0_ring_emit_fence,

	.emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+29 −9
Original line number Diff line number Diff line
@@ -3340,7 +3340,8 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev, 
			  const union dc_tiling_info *tiling_info,

			  const uint64_t info,

			  struct dc_plane_dcc_param *dcc,

			  struct dc_plane_address *address)

			  struct dc_plane_address *address,

			  bool force_disable_dcc)

{

	struct dc *dc = adev->dm.dc;

	struct dc_dcc_surface_param input;
@@ -3352,6 +3353,9 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev, 
	memset(&input, 0, sizeof(input));

	memset(&output, 0, sizeof(output));



	if (force_disable_dcc)

		return 0;



	if (!offset)

		return 0;
@@ -3401,7 +3405,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, 
			     union dc_tiling_info *tiling_info,

			     struct plane_size *plane_size,

			     struct dc_plane_dcc_param *dcc,

			     struct dc_plane_address *address)

			     struct dc_plane_address *address,

			     bool force_disable_dcc)

{

	const struct drm_framebuffer *fb = &afb->base;

	int ret;
@@ -3507,7 +3512,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, 


		ret = fill_plane_dcc_attributes(adev, afb, format, rotation,

						plane_size, tiling_info,

						tiling_flags, dcc, address);

						tiling_flags, dcc, address,

						force_disable_dcc);

		if (ret)

			return ret;

	}
@@ -3599,7 +3605,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 
			    const struct drm_plane_state *plane_state,

			    const uint64_t tiling_flags,

			    struct dc_plane_info *plane_info,

			    struct dc_plane_address *address)

			    struct dc_plane_address *address,

			    bool force_disable_dcc)

{

	const struct drm_framebuffer *fb = plane_state->fb;

	const struct amdgpu_framebuffer *afb =
@@ -3681,7 +3688,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 
					   plane_info->rotation, tiling_flags,

					   &plane_info->tiling_info,

					   &plane_info->plane_size,

					   &plane_info->dcc, address);

					   &plane_info->dcc, address,

					   force_disable_dcc);

	if (ret)

		return ret;
@@ -3704,6 +3712,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, 
	struct dc_plane_info plane_info;

	uint64_t tiling_flags;

	int ret;

	bool force_disable_dcc = false;



	ret = fill_dc_scaling_info(plane_state, &scaling_info);

	if (ret)
@@ -3718,9 +3727,11 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, 
	if (ret)

		return ret;



	force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;

	ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,

					  &plane_info,

					  &dc_plane_state->address);

					  &dc_plane_state->address,

					  force_disable_dcc);

	if (ret)

		return ret;
@@ -5342,6 +5353,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 
	uint64_t tiling_flags;

	uint32_t domain;

	int r;

	bool force_disable_dcc = false;



	dm_plane_state_old = to_dm_plane_state(plane->state);

	dm_plane_state_new = to_dm_plane_state(new_state);
@@ -5400,11 +5412,13 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, 
			dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {

		struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;



		force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;

		fill_plane_buffer_attributes(

			adev, afb, plane_state->format, plane_state->rotation,

			tiling_flags, &plane_state->tiling_info,

			&plane_state->plane_size, &plane_state->dcc,

			&plane_state->address);

			&plane_state->address,

			force_disable_dcc);

	}



	return 0;
@@ -6676,7 +6690,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 
		fill_dc_plane_info_and_addr(

			dm->adev, new_plane_state, tiling_flags,

			&bundle->plane_infos[planes_count],

			&bundle->flip_addrs[planes_count].address);

			&bundle->flip_addrs[planes_count].address,

			false);



		DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n",

				 new_plane_state->plane->index,

				 bundle->plane_infos[planes_count].dcc.enable);



		bundle->surface_updates[planes_count].plane_info =

			&bundle->plane_infos[planes_count];
@@ -8096,7 +8115,8 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm, 
				ret = fill_dc_plane_info_and_addr(

					dm->adev, new_plane_state, tiling_flags,

					plane_info,

					&flip_addr->address);

					&flip_addr->address,

					false);

				if (ret)

					goto cleanup;

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+27 −0
Original line number Diff line number Diff line
@@ -2908,6 +2908,12 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd 
					sizeof(hpd_irq_dpcd_data),

					"Status: ");



		for (i = 0; i < MAX_PIPES; i++) {

			pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];

			if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)

				link->dc->hwss.blank_stream(pipe_ctx);

		}



		for (i = 0; i < MAX_PIPES; i++) {

			pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];

			if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
@@ -2927,6 +2933,12 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd 
		if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

			dc_link_reallocate_mst_payload(link);



		for (i = 0; i < MAX_PIPES; i++) {

			pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];

			if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)

				link->dc->hwss.unblank_stream(pipe_ctx, &previous_link_settings);

		}



		status = false;

		if (out_link_loss)

			*out_link_loss = true;
@@ -4227,6 +4239,21 @@ void dp_set_fec_enable(struct dc_link *link, bool enable) 
void dpcd_set_source_specific_data(struct dc_link *link)

{

	const uint32_t post_oui_delay = 30; // 30ms

	uint8_t dspc = 0;

	enum dc_status ret = DC_ERROR_UNEXPECTED;



	ret = core_link_read_dpcd(link, DP_DOWN_STREAM_PORT_COUNT, &dspc,

				  sizeof(dspc));



	if (ret != DC_OK) {

		DC_LOG_ERROR("Error in DP aux read transaction,"

			     " not writing source specific data\n");

		return;

	}



	/* Return if OUI unsupported */

	if (!(dspc & DP_OUI_SUPPORT))

		return;



	if (!link->dc->vendor_signature.is_valid) {

		struct dpcd_amd_signature amd_signature;

CRA Git | Maintained and supported by SUSTech CRA and CCSE