Commit 465931e7 authored Jun 18, 2020 by Robin Murphy Committed by Heiko Stuebner Jul 08, 2020

clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328"

This reverts commit 82f4b67f.

According to a subsequent revert in the vendor kernel, the original
change was based on unclear documentation and was in fact incorrect.

Emprically, my board's HS200 eMMC at 200MHZ apparently gets lucky with a
phase where this had no impact, but limiting max-frequency to 150MHz to
match the nominal capability of the I/O pins made it virtually unusable,
constantly throwing errors and retuning. With this revert, it starts
behaving perfectly at 150MHz too.

Fixes: 82f4b67f ("clk: rockchip: fix wrong mmc sample phase shift for rk3328")
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://lore.kernel.org/r/c80eb52e34c03f817586b6b7912fbd4e31be9079.1589475794.git.robin.murphy@arm.com

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

parent 0a7f99aa

drivers/clk/rockchip/clk-rk3328.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -808,22 +808,22 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
		MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
		RK3328_SDMMC_CON0, 1),
		MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
		RK3328_SDMMC_CON1, 0),
		RK3328_SDMMC_CON1, 1),

		MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
		RK3328_SDIO_CON0, 1),
		MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
		RK3328_SDIO_CON1, 0),
		RK3328_SDIO_CON1, 1),

		MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
		RK3328_EMMC_CON0, 1),
		MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
		RK3328_EMMC_CON1, 0),
		RK3328_EMMC_CON1, 1),

		MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext",
		RK3328_SDMMC_EXT_CON0, 1),
		MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext",
		RK3328_SDMMC_EXT_CON1, 0),
		RK3328_SDMMC_EXT_CON1, 1),
		};

		static const char *const rk3328_critical_clocks[] __initconst = {