Commit 82f4b67f authored by Ziyuan Xu's avatar Ziyuan Xu Committed by Heiko Stuebner
Browse files

clk: rockchip: fix wrong mmc sample phase shift for rk3328 



mmc sample shift is 0 for RK3328 referring to the TRM.
So fix them.

Fixes: fe3511ad ("clk: rockchip: add clock controller for rk3328")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarZiyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent c14d28e8

drivers/clk/rockchip/clk-rk3328.c

+4 −4
Original line number Diff line number Diff line
@@ -813,22 +813,22 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
	MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",

	    RK3328_SDMMC_CON0, 1),

	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",

	    RK3328_SDMMC_CON1, 1),

	    RK3328_SDMMC_CON1, 0),



	MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",

	    RK3328_SDIO_CON0, 1),

	MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",

	    RK3328_SDIO_CON1, 1),

	    RK3328_SDIO_CON1, 0),



	MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",

	    RK3328_EMMC_CON0, 1),

	MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",

	    RK3328_EMMC_CON1, 1),

	    RK3328_EMMC_CON1, 0),



	MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext",

	    RK3328_SDMMC_EXT_CON0, 1),

	MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext",

	    RK3328_SDMMC_EXT_CON1, 1),

	    RK3328_SDMMC_EXT_CON1, 0),

};



static const char *const rk3328_critical_clocks[] __initconst = {

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