Commit 4646de87 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mailbox-v5.7' of git://git.linaro.org/landing-teams/working/fujitsu/integration 

Pull mailbox updates from Jassi Brar:

 - imx: add support for i.MX8/8X to existing driver

 - mediatek: drop the atomix execution feature, add flush

 - allwinner: new 'msgbox' controller driver

 - armada: misc: drop redundant error print

 - bcm: misc: catch error in probe and snprintf buffer overflow

* tag 'mailbox-v5.7' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: imx: add SCU MU support
  mailbox: imx: restructure code to make easy for new MU
  dt-bindings: mailbox: imx-mu: add SCU MU support
  mailbox: mediatek: remove implementation related to atomic_exec
  mailbox: mediatek: implement flush function
  dt-binding: gce: remove atomic_exec in mboxes property
  maillbox: bcm-flexrm-mailbox: handle cmpl_pool dma allocation failure
  mailbox: sun6i-msgbox: Add a new mailbox driver
  dt-bindings: mailbox: Add a binding for the sun6i msgbox
  mailbox: bcm-pdc: Use scnprintf() for avoiding potential buffer overflow
  mailbox:armada-37xx-rwtm:remove duplicate print in armada_37xx_mbox_probe()
parents c101e9bb 0a67003b

Documentation/devicetree/bindings/mailbox/allwinner,sun6i-a31-msgbox.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/mailbox/allwinner,sun6i-a31-msgbox.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Allwinner sunxi Message Box



maintainers:

  - Samuel Holland <samuel@sholland.org>



description: |

  The hardware message box on sun6i, sun8i, sun9i, and sun50i SoCs is a

  two-user mailbox controller containing 8 unidirectional FIFOs. An interrupt

  is raised for received messages, but software must poll to know when a

  transmitted message has been acknowledged by the remote user. Each FIFO can

  hold four 32-bit messages; when a FIFO is full, clients must wait before

  attempting more transmissions.



  Refer to ./mailbox.txt for generic information about mailbox device-tree

  bindings.



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - allwinner,sun8i-a83t-msgbox

              - allwinner,sun8i-h3-msgbox

              - allwinner,sun9i-a80-msgbox

              - allwinner,sun50i-a64-msgbox

              - allwinner,sun50i-h6-msgbox

          - const: allwinner,sun6i-a31-msgbox

      - const: allwinner,sun6i-a31-msgbox



  reg:

    maxItems: 1



  clocks:

    maxItems: 1

    description: bus clock



  resets:

    maxItems: 1

    description: bus reset



  interrupts:

    maxItems: 1



  '#mbox-cells':

    const: 1

    description: first cell is the channel number (0-7)



required:

  - compatible

  - reg

  - clocks

  - resets

  - interrupts

  - '#mbox-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/sun8i-h3-ccu.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/reset/sun8i-h3-ccu.h>



    msgbox: mailbox@1c17000 {

            compatible = "allwinner,sun8i-h3-msgbox",

                         "allwinner,sun6i-a31-msgbox";

            reg = <0x01c17000 0x1000>;

            clocks = <&ccu CLK_BUS_MSGBOX>;

            resets = <&ccu RST_BUS_MSGBOX>;

            interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

            #mbox-cells = <1>;

    };



...

Documentation/devicetree/bindings/mailbox/fsl,mu.txt

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@@ -23,6 +23,8 @@ Required properties: 
		be included together with SoC specific compatible.

		There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu"

		compatible to support it.

		To communicate with i.MX8 SCU, "fsl,imx8-mu-scu" could be

		used for fast IPC

- reg :		Should contain the registers location and length

- interrupts :	Interrupt number. The interrupt specifier format depends

		on the interrupt controller parent.

Documentation/devicetree/bindings/mailbox/mtk-gce.txt

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@@ -14,13 +14,11 @@ Required properties: 
- interrupts: The interrupt signal from the GCE block

- clock: Clocks according to the common clock binding

- clock-names: Must be "gce" to stand for GCE clock

- #mbox-cells: Should be 3.

	<&phandle channel priority atomic_exec>

- #mbox-cells: Should be 2.

	<&phandle channel priority>

	phandle: Label name of a gce node.

	channel: Channel of mailbox. Be equal to the thread id of GCE.

	priority: Priority of GCE thread.

	atomic_exec: GCE processing continuous packets of commands in atomic

		way.



Required properties for a client device:

- mboxes: Client use mailbox to communicate with GCE, it should have this
@@ -54,8 +52,8 @@ Example for a client device: 


	mmsys: clock-controller@14000000 {

		compatible = "mediatek,mt8173-mmsys";

		mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,

			 <&gce 1 CMDQ_THR_PRIO_LOWEST 1>;

		mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST>,

			 <&gce 1 CMDQ_THR_PRIO_LOWEST>;

		mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF

				CMDQ_EVENT_MUTEX1_STREAM_EOF>;

		mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>,

drivers/mailbox/Kconfig

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@@ -227,4 +227,13 @@ config ZYNQMP_IPI_MBOX 
	  message to the IPI buffer and will access the IPI control

	  registers to kick the other processor or enquire status.



config SUN6I_MSGBOX

	tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box"

	depends on ARCH_SUNXI || COMPILE_TEST

	default ARCH_SUNXI

	help

	  Mailbox implementation for the hardware message box present in

	  various Allwinner SoCs. This mailbox is used for communication

	  between the application CPUs and the power management coprocessor.



endif

drivers/mailbox/Makefile

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@@ -48,3 +48,5 @@ obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o 
obj-$(CONFIG_MTK_CMDQ_MBOX)	+= mtk-cmdq-mailbox.o



obj-$(CONFIG_ZYNQMP_IPI_MBOX)	+= zynqmp-ipi-mailbox.o



obj-$(CONFIG_SUN6I_MSGBOX)	+= sun6i-msgbox.o

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