Commit 0a67003b authored by Peng Fan's avatar Peng Fan Committed by Jassi Brar
Browse files

mailbox: imx: add SCU MU support 



i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A
cores from hardware design, and could not be reused for other purpose.

Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples",
 Passing short messages: Transmit register(s) can be used to pass
 short messages from one to four words in length. For example, when
 a four-word message is desired, only one of the registers needs to
 have its corresponding interrupt enable bit set at the receiver side;
 the message’s first three words are written to the registers whose
 interrupt is masked, and the fourth word is written to the other
 register (which triggers an interrupt at the receiver side).

i.MX8/8X SCU firmware IPC is an implementation of passing short
messages. But current imx-mailbox driver only support one word
message, i.MX8/8X linux side firmware has to request four TX
and four RX to support IPC to SCU firmware. This is low efficent
and more interrupts triggered compared with one TX and
one RX.

To make SCU MU work,
  - parse the size of msg.
  - Only enable TR0/RR0 interrupt for transmit/receive message.
  - For TX/RX, only support one TX channel and one RX channel
  - For RX, support receive msg larger than 4 u32 words.
  - Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB.

Reviewed-by: default avatarOleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarJassi Brar <jaswinder.singh@linaro.org>
parent 63b38357

drivers/mailbox/imx-mailbox.c

+155 −0
Original line number Diff line number Diff line
@@ -4,8 +4,10 @@ 
 */



#include <linux/clk.h>

#include <linux/firmware/imx/ipc.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/iopoll.h>

#include <linux/kernel.h>

#include <linux/mailbox_controller.h>

#include <linux/module.h>
@@ -27,6 +29,8 @@ 
#define IMX_MU_xCR_GIRn(x)	BIT(16 + (3 - (x)))



#define IMX_MU_CHANS		16

/* TX0/RX0/RXDB[0-3] */

#define IMX_MU_SCU_CHANS	6

#define IMX_MU_CHAN_NAME_SIZE	20



enum imx_mu_chan_type {
@@ -36,6 +40,11 @@ enum imx_mu_chan_type { 
	IMX_MU_TYPE_RXDB,	/* Rx doorbell */

};



struct imx_sc_rpc_msg_max {

	struct imx_sc_rpc_msg hdr;

	u32 data[7];

};



struct imx_mu_con_priv {

	unsigned int		idx;

	char			irq_desc[IMX_MU_CHAN_NAME_SIZE];
@@ -134,6 +143,83 @@ static int imx_mu_generic_rx(struct imx_mu_priv *priv, 
	return 0;

}



static int imx_mu_scu_tx(struct imx_mu_priv *priv,

			 struct imx_mu_con_priv *cp,

			 void *data)

{

	struct imx_sc_rpc_msg_max *msg = data;

	u32 *arg = data;

	int i, ret;

	u32 xsr;



	switch (cp->type) {

	case IMX_MU_TYPE_TX:

		if (msg->hdr.size > sizeof(*msg)) {

			/*

			 * The real message size can be different to

			 * struct imx_sc_rpc_msg_max size

			 */

			dev_err(priv->dev, "Exceed max msg size (%zu) on TX, got: %i\n", sizeof(*msg), msg->hdr.size);

			return -EINVAL;

		}



		for (i = 0; i < 4 && i < msg->hdr.size; i++)

			imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);

		for (; i < msg->hdr.size; i++) {

			ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,

						 xsr,

						 xsr & IMX_MU_xSR_TEn(i % 4),

						 0, 100);

			if (ret) {

				dev_err(priv->dev, "Send data index: %d timeout\n", i);

				return ret;

			}

			imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);

		}



		imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);

		break;

	default:

		dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);

		return -EINVAL;

	}



	return 0;

}



static int imx_mu_scu_rx(struct imx_mu_priv *priv,

			 struct imx_mu_con_priv *cp)

{

	struct imx_sc_rpc_msg_max msg;

	u32 *data = (u32 *)&msg;

	int i, ret;

	u32 xsr;



	imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));

	*data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);



	if (msg.hdr.size > sizeof(msg)) {

		dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n",

			sizeof(msg), msg.hdr.size);

		return -EINVAL;

	}



	for (i = 1; i < msg.hdr.size; i++) {

		ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr,

					 xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);

		if (ret) {

			dev_err(priv->dev, "timeout read idx %d\n", i);

			return ret;

		}

		*data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);

	}



	imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);

	mbox_chan_received_data(cp->chan, (void *)&msg);



	return 0;

}



static void imx_mu_txdb_tasklet(unsigned long data)

{

	struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
@@ -263,6 +349,42 @@ static const struct mbox_chan_ops imx_mu_ops = { 
	.shutdown = imx_mu_shutdown,

};



static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox,

					  const struct of_phandle_args *sp)

{

	u32 type, idx, chan;



	if (sp->args_count != 2) {

		dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);

		return ERR_PTR(-EINVAL);

	}



	type = sp->args[0]; /* channel type */

	idx = sp->args[1]; /* index */



	switch (type) {

	case IMX_MU_TYPE_TX:

	case IMX_MU_TYPE_RX:

		if (idx != 0)

			dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);

		chan = type;

		break;

	case IMX_MU_TYPE_RXDB:

		chan = 2 + idx;

		break;

	default:

		dev_err(mbox->dev, "Invalid chan type: %d\n", type);

		return NULL;

	}



	if (chan >= mbox->num_chans) {

		dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);

		return ERR_PTR(-EINVAL);

	}



	return &mbox->chans[chan];

}



static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,

				       const struct of_phandle_args *sp)

{
@@ -310,6 +432,28 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv) 
	imx_mu_write(priv, 0, priv->dcfg->xCR);

}



static void imx_mu_init_scu(struct imx_mu_priv *priv)

{

	unsigned int i;



	for (i = 0; i < IMX_MU_SCU_CHANS; i++) {

		struct imx_mu_con_priv *cp = &priv->con_priv[i];



		cp->idx = i < 2 ? 0 : i - 2;

		cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;

		cp->chan = &priv->mbox_chans[i];

		priv->mbox_chans[i].con_priv = cp;

		snprintf(cp->irq_desc, sizeof(cp->irq_desc),

			 "imx_mu_chan[%i-%i]", cp->type, cp->idx);

	}



	priv->mbox.num_chans = IMX_MU_SCU_CHANS;

	priv->mbox.of_xlate = imx_mu_scu_xlate;



	/* Set default MU configuration */

	imx_mu_write(priv, 0, priv->dcfg->xCR);

}



static int imx_mu_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;
@@ -396,9 +540,20 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { 
	.xCR	= 0x64,

};



static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {

	.tx	= imx_mu_scu_tx,

	.rx	= imx_mu_scu_rx,

	.init	= imx_mu_init_scu,

	.xTR	= {0x0, 0x4, 0x8, 0xc},

	.xRR	= {0x10, 0x14, 0x18, 0x1c},

	.xSR	= 0x20,

	.xCR	= 0x24,

};



static const struct of_device_id imx_mu_dt_ids[] = {

	{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },

	{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },

	{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },

	{ },

};

MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);

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