Commit 461ea6ab authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-qcom-rpmh', 'clk-gpio-sleep', 'clk-stm32mp1',... 

Merge branches 'clk-qcom-rpmh', 'clk-gpio-sleep', 'clk-stm32mp1', 'clk-qcom-qcs404' and 'clk-actions-s500' into clk-next

 - IPA clk support on Qualcomm RPMh clk controllers
 - Support sleeping gpios in clk-gpio type
 - Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.)
 - Actions Semi S500 SoC clk support

* clk-qcom-rpmh:
  clk: qcom: clk-rpmh: Add IPA clock support

* clk-gpio-sleep:
  clk: clk-gpio: add support for sleeping GPIOs in gpio-gate-clk

* clk-stm32mp1:
  dt-bindings: clock: remove unused definition for stm32mp1
  clk: stm32mp1: fix bit width of hse_rtc divider
  clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag
  clk: stm32mp1: fix HSI divider flag
  clk: stm32mp1: fix mcu divider table
  clk: stm32mp1: set ck_csi as critical clock
  clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks
  clk: stm32mp1: parent clocks update

* clk-qcom-qcs404:
  clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock
  clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs
  clk: qcom: remove empty lines in clk-rcg.h

* clk-actions-s500:
  clk: actions: Add clock driver for S500 SoC
  dt-bindings: clock: Add DT bindings for Actions Semi S500 CMU
  clk: actions: Add configurable PLL delay
parents e7faa095 04053f4d c0189fee 585fc46b 9d575719 ed6b4795

Documentation/devicetree/bindings/clock/actions,owl-cmu.txt

+4 −3
Original line number Diff line number Diff line
@@ -2,13 +2,14 @@ 


The Actions Semi Owl Clock Management Unit generates and supplies clock

to various controllers within the SoC. The clock binding described here is

applicable to S900 and S700 SoC's.

applicable to S900, S700 and S500 SoC's.



Required Properties:



- compatible: should be one of the following,

	"actions,s900-cmu"

	"actions,s700-cmu"

	"actions,s500-cmu"

- reg: physical base address of the controller and length of memory mapped

  region.

- clocks: Reference to the parent clocks ("hosc", "losc")
@@ -19,8 +20,8 @@ Each clock is assigned an identifier, and client nodes can use this identifier 
to specify the clock which they consume.



All available clocks are defined as preprocessor macros in corresponding

dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h header and can be

used in device tree sources.

dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or

actions,s500-cmu.h header and can be used in device tree sources.



External clocks:

drivers/clk/actions/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -9,6 +9,11 @@ if CLK_ACTIONS 


# SoC Drivers



config CLK_OWL_S500

	bool "Support for the Actions Semi OWL S500 clocks"

	depends on ARCH_ACTIONS || COMPILE_TEST

	default ARCH_ACTIONS



config CLK_OWL_S700

	bool "Support for the Actions Semi OWL S700 clocks"

	depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST

drivers/clk/actions/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -10,5 +10,6 @@ clk-owl-y += owl-pll.o 
clk-owl-y			+= owl-reset.o



# SoC support

obj-$(CONFIG_CLK_OWL_S500)	+= owl-s500.o

obj-$(CONFIG_CLK_OWL_S700)	+= owl-s700.o

obj-$(CONFIG_CLK_OWL_S900)	+= owl-s900.o

drivers/clk/actions/owl-pll.c

+1 −1
Original line number Diff line number Diff line
@@ -179,7 +179,7 @@ static int owl_pll_set_rate(struct clk_hw *hw, unsigned long rate, 


	regmap_write(common->regmap, pll_hw->reg, reg);



	udelay(PLL_STABILITY_WAIT_US);

	udelay(pll_hw->delay);



	return 0;

}

drivers/clk/actions/owl-pll.h

+24 −6
Original line number Diff line number Diff line
@@ -13,6 +13,8 @@ 


#include "owl-common.h"



#define OWL_PLL_DEF_DELAY	50



/* last entry should have rate = 0 */

struct clk_pll_table {

	unsigned int		val;
@@ -27,6 +29,7 @@ struct owl_pll_hw { 
	u8			width;

	u8			min_mul;

	u8			max_mul;

	u8			delay;

	const struct clk_pll_table *table;

};
@@ -36,7 +39,7 @@ struct owl_pll { 
};



#define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,			\

		   _width, _min_mul, _max_mul, _table)			\

		   _width, _min_mul, _max_mul, _delay, _table)		\

	{								\

		.reg		= _reg,					\

		.bfreq		= _bfreq,				\
@@ -45,6 +48,7 @@ struct owl_pll { 
		.width		= _width,				\

		.min_mul	= _min_mul,				\

		.max_mul	= _max_mul,				\

		.delay		= _delay,				\

		.table		= _table,				\

	}
@@ -52,8 +56,8 @@ struct owl_pll { 
		_shift, _width, _min_mul, _max_mul, _table, _flags)	\

	struct owl_pll _struct = {					\

		.pll_hw	= OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,	\

				     _width, _min_mul,			\

				     _max_mul, _table),			\

				     _width, _min_mul, _max_mul,	\

				     OWL_PLL_DEF_DELAY,	_table),	\

		.common = {						\

			.regmap = NULL,					\

			.hw.init = CLK_HW_INIT(_name,			\
@@ -67,8 +71,23 @@ struct owl_pll { 
		_shift, _width, _min_mul, _max_mul, _table, _flags)	\

	struct owl_pll _struct = {					\

		.pll_hw	= OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,	\

				     _width, _min_mul,			\

				     _max_mul, _table),			\

				     _width, _min_mul, _max_mul,	\

				     OWL_PLL_DEF_DELAY,	_table),	\

		.common = {						\

			.regmap = NULL,					\

			.hw.init = CLK_HW_INIT_NO_PARENT(_name,		\

					       &owl_pll_ops,		\

					       _flags),			\

		},							\

	}



#define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx,	\

		_shift, _width, _min_mul, _max_mul, _delay, _table,	\

		_flags)							\

	struct owl_pll _struct = {					\

		.pll_hw	= OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,	\

				     _width, _min_mul,  _max_mul,	\

				     _delay, _table),			\

		.common = {						\

			.regmap = NULL,					\

			.hw.init = CLK_HW_INIT_NO_PARENT(_name,		\
@@ -78,7 +97,6 @@ struct owl_pll { 
	}



#define mul_mask(m)		((1 << ((m)->width)) - 1)

#define PLL_STABILITY_WAIT_US	(50)



static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw)

{

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