Commit e7faa095 authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-imx', 'clk-samsung', 'clk-ti', 'clk-uniphier-gear' and... 

Merge branches 'clk-imx', 'clk-samsung', 'clk-ti', 'clk-uniphier-gear' and 'clk-mmp2-lcdc' into clk-next

 - Split LCDC into two clks on the Marvell MMP2 SoC

* clk-imx:
  clk: imx8mq: add GPIO clocks to clock tree
  clk: imx: Refactor entire sccg pll clk
  clk: imx: scu: add cpu frequency scaling support
  clk: imx: imx8mm: Mark init function __init
  clk: imx8mq: Add the missing ARM clock
  dt-bindings: imx8mq-clock: Add the missing ARM clock
  clk: imx: imx8mq: Fix the rate propagation for arm pll
  clk: imx8mq: Add support for the CLKO1 clock
  clk: imx8mq: Fix the CLKO2 source select list
  clk: imx8mq: Add missing M4 clocks
  clk: imx: Add clock driver support for imx8mm
  dt-bindings: imx: Add clock binding doc for imx8mm
  clk: imx: Add PLLs driver for imx8mm soc
  clk: imx5: add imx5_SCC2_IPG_GATE
  clk: imx: scu: add set parent support
  clk: imx: scu: add fallback compatible string support
  clk: imx8mq: Make parent names arrays const pointers
  clk: imx: Make parents const pointer in mux wrappers
  clk: imx: Make parent_names const pointer in composite-8m

* clk-samsung:
  clk: samsung: s3c2443: Mark expected switch fall-through
  clk: samsung: exynos5: Fix kfree() of const memory on setting driver_override
  clk: samsung: exynos5: Fix possible NULL pointer exception on platform_device_alloc() failure
  clk: samsung: exynos5433: Add selected IMEM clocks
  clk: samsung: dt-bindings: Document Exynos5433 IMEM CMU
  clk: samsung: exynos5433: Fix name typo in sssx
  clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocks
  clk: samsung: dt-bindings: Add Exynos5433 IMEM CMU clock IDs

* clk-ti:
  clk: clk-twl6040: Fix imprecise external abort for pdmclk
  ARM: OMAP2+: hwmod: disable ick autoidling when a hwmod requires that
  clk: ti: check clock type before doing autoidle ops
  clk: ti: add a usecount for autoidle
  clk: ti: generalize the init sequence of clk_hw_omap clocks
  clk: ti: remove usage of CLK_IS_BASIC
  clk: ti: add new API for checking if a provided clock is an OMAP clock
  clk: ti: move clk_hw_omap list handling under generic part of the driver

* clk-uniphier-gear:
  clk: uniphier: Fix update register for CPU-gear

* clk-mmp2-lcdc:
  clk: mmp2: separate LCDC peripheral clk form the display clock
  dt-bindings: marvell,mmp2: Add clock id for the LCDC clock
parents 3f8e7e72 0c91c11c 0612fe60 5ae51d67 52128223 0ea8cbc1

Documentation/devicetree/bindings/clock/exynos5433-clock.txt

+23 −0
Original line number Diff line number Diff line
@@ -50,6 +50,8 @@ Required Properties: 
    IPs.

  - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1

    which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.

  - "samsung,exynos5433-cmu-imem"   - clock controller compatible for CMU_IMEM

    which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.



- reg: physical base address of the controller and length of memory mapped

  region.
@@ -168,6 +170,12 @@ Required Properties: 
		- aclk_cam1_400

		- aclk_cam1_552



	Input clocks for imem clock controller:

		- oscclk

		- aclk_imem_sssx_266

		- aclk_imem_266

		- aclk_imem_200



Optional properties:

  - power-domains: a phandle to respective power domain node as described by

	generic PM domain bindings (see power/power_domain.txt for more
@@ -469,6 +477,21 @@ Example 2: Examples of clock controller nodes are listed below. 
		power-domains = <&pd_cam1>;

	};



	cmu_imem: clock-controller@11060000 {

		compatible = "samsung,exynos5433-cmu-imem";

		reg = <0x11060000 0x1000>;

		#clock-cells = <1>;



		clock-names = "oscclk",

			"aclk_imem_sssx_266",

			"aclk_imem_266",

			"aclk_imem_200";

		clocks = <&xxti>,

			<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,

			<&cmu_top CLK_DIV_ACLK_IMEM_266>,

			<&cmu_top CLK_DIV_ACLK_IMEM_200>;

	};



Example 3: UART controller node that consumes the clock generated by the clock

	   controller.

Documentation/devicetree/bindings/clock/imx8mm-clock.txt

0 → 100644
+29 −0
Original line number Diff line number Diff line 
* Clock bindings for NXP i.MX8M Mini



Required properties:

- compatible: Should be "fsl,imx8mm-ccm"

- reg: Address and length of the register set

- #clock-cells: Should be <1>

- clocks: list of clock specifiers, must contain an entry for each required

          entry in clock-names

- clock-names: should include the following entries:

    - "osc_32k"

    - "osc_24m"

    - "clk_ext1"

    - "clk_ext2"

    - "clk_ext3"

    - "clk_ext4"



clk: clock-controller@30380000 {

	compatible = "fsl,imx8mm-ccm";

	reg = <0x0 0x30380000 0x0 0x10000>;

	#clock-cells = <1>;

	clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,

		 <&clk_ext3>, <&clk_ext4>;

	clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",

		      "clk_ext3", "clk_ext4";

};



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h

for the full list of i.MX8M Mini clock IDs.

arch/arm/mach-omap2/omap_hwmod.c

+12 −4
Original line number Diff line number Diff line
@@ -1002,9 +1002,11 @@ static int _enable_clocks(struct omap_hwmod *oh) 
		clk_enable(oh->_clk);



	list_for_each_entry(os, &oh->slave_ports, node) {

		if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))

		if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) {

			omap2_clk_deny_idle(os->_clk);

			clk_enable(os->_clk);

		}

	}



	/* The opt clocks are controlled by the device driver. */
@@ -1055,8 +1057,10 @@ static int _disable_clocks(struct omap_hwmod *oh) 
		clk_disable(oh->_clk);



	list_for_each_entry(os, &oh->slave_ports, node) {

		if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))

		if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) {

			clk_disable(os->_clk);

			omap2_clk_allow_idle(os->_clk);

		}

	}



	if (oh->flags & HWMOD_OPT_CLKS_NEEDED)
@@ -2436,9 +2440,13 @@ static void _setup_iclk_autoidle(struct omap_hwmod *oh) 
			continue;



		if (os->flags & OCPIF_SWSUP_IDLE) {

			/* XXX omap_iclk_deny_idle(c); */

			/*

			 * we might have multiple users of one iclk with

			 * different requirements, disable autoidle when

			 * the module is enabled, e.g. dss iclk

			 */

		} else {

			/* XXX omap_iclk_allow_idle(c); */

			/* we are enabling autoidle afterwards anyways */

			clk_enable(os->_clk);

		}

	}

drivers/clk/clk-twl6040.c

+51 −2
Original line number Diff line number Diff line
@@ -41,6 +41,43 @@ static int twl6040_pdmclk_is_prepared(struct clk_hw *hw) 
	return pdmclk->enabled;

}



static int twl6040_pdmclk_reset_one_clock(struct twl6040_pdmclk *pdmclk,

					  unsigned int reg)

{

	const u8 reset_mask = TWL6040_HPLLRST;	/* Same for HPPLL and LPPLL */

	int ret;



	ret = twl6040_set_bits(pdmclk->twl6040, reg, reset_mask);

	if (ret < 0)

		return ret;



	ret = twl6040_clear_bits(pdmclk->twl6040, reg, reset_mask);

	if (ret < 0)

		return ret;



	return 0;

}



/*

 * TWL6040A2 Phoenix Audio IC erratum #6: "PDM Clock Generation Issue At

 * Cold Temperature". This affects cold boot and deeper idle states it

 * seems. The workaround consists of resetting HPPLL and LPPLL.

 */

static int twl6040_pdmclk_quirk_reset_clocks(struct twl6040_pdmclk *pdmclk)

{

	int ret;



	ret = twl6040_pdmclk_reset_one_clock(pdmclk, TWL6040_REG_HPPLLCTL);

	if (ret)

		return ret;



	ret = twl6040_pdmclk_reset_one_clock(pdmclk, TWL6040_REG_LPPLLCTL);

	if (ret)

		return ret;



	return 0;

}



static int twl6040_pdmclk_prepare(struct clk_hw *hw)

{

	struct twl6040_pdmclk *pdmclk = container_of(hw, struct twl6040_pdmclk,
@@ -48,9 +85,21 @@ static int twl6040_pdmclk_prepare(struct clk_hw *hw) 
	int ret;



	ret = twl6040_power(pdmclk->twl6040, 1);

	if (!ret)

	if (ret)

		return ret;



	ret = twl6040_pdmclk_quirk_reset_clocks(pdmclk);

	if (ret)

		goto out_err;



	pdmclk->enabled = 1;



	return 0;



out_err:

	dev_err(pdmclk->dev, "%s: error %i\n", __func__, ret);

	twl6040_power(pdmclk->twl6040, 0);



	return ret;

}

drivers/clk/imx/Kconfig

+6 −0
Original line number Diff line number Diff line
@@ -8,6 +8,12 @@ config MXC_CLK_SCU 
	bool

	depends on IMX_SCU



config CLK_IMX8MM

	bool "IMX8MM CCM Clock Driver"

	depends on ARCH_MXC && ARM64

	help

	    Build the driver for i.MX8MM CCM Clock Driver



config CLK_IMX8MQ

	bool "IMX8MQ CCM Clock Driver"

	depends on ARCH_MXC && ARM64

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