Commit 45eedc0e authored by Andrzej Hajda's avatar Andrzej Hajda Committed by Krzysztof Kozlowski
Browse files

arm64: dts: exynos: add DSD/GSD clocks to DECONs and GSCALERs of Exynos5433 



To support local paths both DECON and GSCALER should enable respective
Smart Deck clocks DSD and GSD on Exynos5433.

Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent 7698ffaf

arch/arm64/boot/dts/exynos/exynos5433.dtsi

+15 −10
Original line number Diff line number Diff line
@@ -848,12 +848,13 @@ 
				<&cmu_disp CLK_ACLK_XIU_DECON1X>,

				<&cmu_disp CLK_PCLK_SMMU_DECON1X>,

				<&cmu_disp CLK_SCLK_DECON_VCLK>,

				<&cmu_disp CLK_SCLK_DECON_ECLK>;

				<&cmu_disp CLK_SCLK_DECON_ECLK>,

				<&cmu_disp CLK_SCLK_DSD>;

			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",

				"aclk_xiu_decon0x", "pclk_smmu_decon0x",

				"aclk_smmu_decon1x", "aclk_xiu_decon1x",

				"pclk_smmu_decon1x", "sclk_decon_vclk",

				"sclk_decon_eclk";

				"sclk_decon_eclk", "dsd";

			power-domains = <&pd_disp>;

			interrupt-names = "fifo", "vsync", "lcd_sys";

			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
@@ -890,12 +891,13 @@ 
				 <&cmu_disp CLK_ACLK_XIU_TV1X>,

				 <&cmu_disp CLK_PCLK_SMMU_TV1X>,

				 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,

				 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;

				 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>,

				 <&cmu_disp CLK_SCLK_DSD>;

			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",

				      "aclk_xiu_decon0x", "pclk_smmu_decon0x",

				      "aclk_smmu_decon1x", "aclk_xiu_decon1x",

				      "pclk_smmu_decon1x", "sclk_decon_vclk",

				      "sclk_decon_eclk";

				      "sclk_decon_eclk", "dsd";

			samsung,disp-sysreg = <&syscon_disp>;

			power-domains = <&pd_disp>;

			interrupt-names = "fifo", "vsync", "lcd_sys";
@@ -1022,11 +1024,12 @@ 
			reg = <0x13c00000 0x1000>;

			interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "pclk", "aclk", "aclk_xiu",

				      "aclk_gsclbend";

				      "aclk_gsclbend", "gsd";

			clocks = <&cmu_gscl CLK_PCLK_GSCL0>,

				 <&cmu_gscl CLK_ACLK_GSCL0>,

				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,

				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;

				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,

				 <&cmu_gscl CLK_ACLK_GSD>;

			iommus = <&sysmmu_gscl0>;

			power-domains = <&pd_gscl>;

		};
@@ -1036,11 +1039,12 @@ 
			reg = <0x13c10000 0x1000>;

			interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "pclk", "aclk", "aclk_xiu",

				      "aclk_gsclbend";

				      "aclk_gsclbend", "gsd";

			clocks = <&cmu_gscl CLK_PCLK_GSCL1>,

				 <&cmu_gscl CLK_ACLK_GSCL1>,

				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,

				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;

				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,

				 <&cmu_gscl CLK_ACLK_GSD>;

			iommus = <&sysmmu_gscl1>;

			power-domains = <&pd_gscl>;

		};
@@ -1050,11 +1054,12 @@ 
			reg = <0x13c20000 0x1000>;

			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "pclk", "aclk", "aclk_xiu",

				      "aclk_gsclbend";

				      "aclk_gsclbend", "gsd";

			clocks = <&cmu_gscl CLK_PCLK_GSCL2>,

				 <&cmu_gscl CLK_ACLK_GSCL2>,

				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,

				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;

				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,

				 <&cmu_gscl CLK_ACLK_GSD>;

			iommus = <&sysmmu_gscl2>;

			power-domains = <&pd_gscl>;

		};

CRA Git | Maintained and supported by SUSTech CRA and CCSE