arm64: dts: exynos: configure GSCALER related clocks on TM2

	assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;

};

&cmu_mif {

	assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;

	assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;

	assigned-clock-rates = <0>, <333000000>;

};

&cmu_mscl {

	assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,

			  <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,

			  <&cmu_disp CLK_MOUT_DISP_PLL>,

			  <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,

			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,

			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;

			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>,

			  <&cmu_disp CLK_MOUT_SCLK_DSD_USER>;

	assigned-clock-parents = <0>, <0>,

				 <&cmu_mif CLK_ACLK_DISP_333>,

				 <&cmu_mif CLK_SCLK_DSIM0_DISP>,

				 <&cmu_disp CLK_FOUT_DISP_PLL>,

				 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,

				 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,

				 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;

				 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,

				 <&cmu_mif CLK_SCLK_DSD_DISP>;

	assigned-clock-rates = <250000000>, <400000000>;

};