Commit 45ba3875 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-allwinner', 'clk-rockchip', 'clk-tegra', 'clk-berlin' and... 

Merge branches 'clk-allwinner', 'clk-rockchip', 'clk-tegra', 'clk-berlin' and 'clk-qcom-mmagic' into clk-next

* clk-allwinner:
  clk: sunxi-ng: r40: export a regmap to access the GMAC register
  clk: sunxi-ng: r40: rewrite init code to a platform driver
  clk: sunxi-ng: add support for H6 PRCM CCU

* clk-rockchip:
  clk: rockchip: remove deprecated gate-clk code and dt-binding
  clk: rockchip: use match_string() helper

* clk-tegra:
  clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
  clk: tegra20: Correct parents of CDEV1/2 clocks
  clk: tegra20: Add DEV1/DEV2 OSC dividers

* clk-berlin:
  clk: berlin: switch to SPDX license identifier

* clk-qcom-mmagic:
  clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled
  clk: qcom: Register the gdscs before the clocks
  clk: qcom: gdsc: Add support for ALWAYS_ON gdscs
parents 7fa50aa5 f40cc01e 533dfd60 70b7e55a 3504395f 7705bb71

Documentation/devicetree/bindings/clock/rockchip.txt

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Device Tree Clock bindings for arch-rockchip



This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt



== Gate clocks ==



These bindings are deprecated!

Please use the soc specific CRU bindings instead.



The gate registers form a continuos block which makes the dt node

structure a matter of taste, as either all gates can be put into

one gate clock spanning all registers or they can be divided into

the 10 individual gates containing 16 clocks each.

The code supports both approaches.



Required properties:

- compatible : "rockchip,rk2928-gate-clk"

- reg : shall be the control register address(es) for the clock.

- #clock-cells : from common clock binding; shall be set to 1

- clock-output-names : the corresponding gate names that the clock controls

- clocks : should contain the parent clock for each individual gate,

  therefore the number of clocks elements should match the number of

  clock-output-names



Example using multiple gate clocks:



		clk_gates0: gate-clk@200000d0 {

			compatible = "rockchip,rk2928-gate-clk";

			reg = <0x200000d0 0x4>;

			clocks = <&dummy>, <&dummy>,

				 <&dummy>, <&dummy>,

				 <&dummy>, <&dummy>,

				 <&dummy>, <&dummy>,

				 <&dummy>, <&dummy>,

				 <&dummy>, <&dummy>,

				 <&dummy>, <&dummy>,

				 <&dummy>, <&dummy>;



			clock-output-names =

				"gate_core_periph", "gate_cpu_gpll",

				"gate_ddrphy", "gate_aclk_cpu",

				"gate_hclk_cpu", "gate_pclk_cpu",

				"gate_atclk_cpu", "gate_i2s0",

				"gate_i2s0_frac", "gate_i2s1",

				"gate_i2s1_frac", "gate_i2s2",

				"gate_i2s2_frac", "gate_spdif",

				"gate_spdif_frac", "gate_testclk";



			#clock-cells = <1>;

		};



		clk_gates1: gate-clk@200000d4 {

			compatible = "rockchip,rk2928-gate-clk";

			reg = <0x200000d4 0x4>;

			clocks = <&xin24m>, <&xin24m>,

				 <&xin24m>, <&dummy>,

				 <&dummy>, <&xin24m>,

				 <&xin24m>, <&dummy>,

				 <&xin24m>, <&dummy>,

				 <&xin24m>, <&dummy>,

				 <&xin24m>, <&dummy>,

				 <&xin24m>, <&dummy>;



			clock-output-names =

				"gate_timer0", "gate_timer1",

				"gate_timer2", "gate_jtag",

				"gate_aclk_lcdc1_src", "gate_otgphy0",

				"gate_otgphy1", "gate_ddr_gpll",

				"gate_uart0", "gate_frac_uart0",

				"gate_uart1", "gate_frac_uart1",

				"gate_uart2", "gate_frac_uart2",

				"gate_uart3", "gate_frac_uart3";



			#clock-cells = <1>;

		};

Documentation/devicetree/bindings/clock/sunxi-ccu.txt

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@@ -21,6 +21,7 @@ Required properties : 
		- "allwinner,sun50i-a64-r-ccu"

		- "allwinner,sun50i-h5-ccu"

		- "allwinner,sun50i-h6-ccu"

		- "allwinner,sun50i-h6-r-ccu"

		- "nextthing,gr8-ccu"



- reg: Must contain the registers base address and length
@@ -35,7 +36,7 @@ Required properties : 
For the main CCU on H6, one more clock is needed:

- "iosc": the SoC's internal frequency oscillator



For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:

For the PRCM CCUs on A83T/H3/A64/H6, two more clocks are needed:

- "pll-periph": the SoC's peripheral PLL from the main CCU

- "iosc": the SoC's internal frequency oscillator

drivers/clk/berlin/berlin2-avpll.c

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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2014 Marvell Technology Group Ltd.

 *

 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

 * Alexandre Belloni <alexandre.belloni@free-electrons.com>

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */

#include <linux/clk-provider.h>

#include <linux/io.h>

drivers/clk/berlin/berlin2-avpll.h

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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2014 Marvell Technology Group Ltd.

 *

 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

 * Alexandre Belloni <alexandre.belloni@free-electrons.com>

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */

#ifndef __BERLIN2_AVPLL_H

#define __BERLIN2_AVPLL_H

drivers/clk/berlin/berlin2-div.c

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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2014 Marvell Technology Group Ltd.

 *

 * Alexandre Belloni <alexandre.belloni@free-electrons.com>

 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */

#include <linux/bitops.h>

#include <linux/clk-provider.h>

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