Commit 7fa50aa5 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi',... 

Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', 'clk-mtk-mali' and 'clk-imx6ul-ccosr' into clk-next

* clk-hisi-usb:
  clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC

* clk-silent-bulk:
  clk: bulk: silently error out on EPROBE_DEFER

* clk-mtk-hdmi:
  clk: mediatek: correct the clocks for MT2701 HDMI PHY module

* clk-mtk-mali:
  clk: mediatek: add g3dsys support for MT2701 and MT7623
  dt-bindings: reset: mediatek: add entry for Mali-450 node to refer
  dt-bindings: clock: mediatek: add entry for Mali-450 node to refer
  dt-bindings: clock: mediatek: add g3dsys bindings

* clk-imx6ul-ccosr:
  clk: imx: Add new clo01 and clo2 controlled by CCOSR
parents b7c82cec 80820a7b 329470f2 bf61099a a11ca689 f5a4670d

Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt

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+30 −0
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MediaTek g3dsys controller

============================



The MediaTek g3dsys controller provides various clocks and reset controller to

the GPU.



Required Properties:



- compatible: Should be:

	- "mediatek,mt2701-g3dsys", "syscon":

		for MT2701 SoC

	- "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":

		for MT7623 SoC

- #clock-cells: Must be 1

- #reset-cells: Must be 1



The g3dsys controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt

The available clocks are defined in dt-bindings/clock/mt*-clk.h.



Example:



g3dsys: clock-controller@13000000 {

	compatible = "mediatek,mt7623-g3dsys",

		     "mediatek,mt2701-g3dsys",

		     "syscon";

	reg = <0 0x13000000 0 0x200>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};

drivers/clk/clk-bulk.c

+3 −2
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ int __must_check clk_bulk_get(struct device *dev, int num_clks, 
		clks[i].clk = clk_get(dev, clks[i].id);

		if (IS_ERR(clks[i].clk)) {

			ret = PTR_ERR(clks[i].clk);

			if (ret != -EPROBE_DEFER)

				dev_err(dev, "Failed to get clk '%s': %d\n",

					clks[i].id, ret);

			clks[i].clk = NULL;

drivers/clk/hisilicon/crg-hi3798cv200.c

+17 −0
Original line number Diff line number Diff line
@@ -186,6 +186,23 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { 
		CLK_SET_RATE_PARENT, 0xbc, 0, 0 },

	{ HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",

		CLK_SET_RATE_PARENT, 0xbc, 2, 0 },

	/* USB3 */

	{ HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL,

		CLK_SET_RATE_PARENT, 0xb0, 0, 0 },

	{ HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL,

		CLK_SET_RATE_PARENT, 0xb0, 4, 0 },

	{ HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL,

		CLK_SET_RATE_PARENT, 0xb0, 3, 0 },

	{ HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL,

		CLK_SET_RATE_PARENT, 0xb0, 2, 0 },

	{ HISTB_USB3_BUS_CLK1, "clk_u3_bus1", NULL,

		CLK_SET_RATE_PARENT, 0xb0, 16, 0 },

	{ HISTB_USB3_UTMI_CLK1, "clk_u3_utmi1", NULL,

		CLK_SET_RATE_PARENT, 0xb0, 20, 0 },

	{ HISTB_USB3_PIPE_CLK1, "clk_u3_pipe1", NULL,

		CLK_SET_RATE_PARENT, 0xb0, 19, 0 },

	{ HISTB_USB3_SUSPEND_CLK1, "clk_u3_suspend1", NULL,

		CLK_SET_RATE_PARENT, 0xb0, 18, 0 },

};



static struct hisi_clock_data *hi3798cv200_clk_register(

drivers/clk/imx/clk-imx6ul.c

+18 −0
Original line number Diff line number Diff line
@@ -68,6 +68,13 @@ static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", " 
static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };

static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };

static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };

static const char *cko1_sels[] = { "dummy", "dummy", "dummy", "dummy", "dummy", "axi", "enfc", "dummy", "dummy",

				   "dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };

static const char *cko2_sels[] = { "dummy", "dummy", "dummy", "usdhc1", "dummy", "dummy", "ecspi_root", "dummy",

				   "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "osc", "dummy",

				   "dummy", "usdhc2", "sai1", "sai2", "sai3", "dummy", "dummy", "can_root",

				   "dummy", "dummy", "dummy", "dummy", "uart_serial", "spdif", "dummy", "dummy", };

static const char *cko_sels[] = { "cko1", "cko2", };



static struct clk *clks[IMX6UL_CLK_END];

static struct clk_onecell_data clk_data;
@@ -273,6 +280,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clks[IMX6UL_CLK_LDB_DI0_DIV_SEL]  = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));

	clks[IMX6UL_CLK_LDB_DI1_DIV_SEL]  = imx_clk_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));



	clks[IMX6UL_CLK_CKO1_SEL]	  = imx_clk_mux("cko1_sel", base + 0x60, 0,  4, cko1_sels, ARRAY_SIZE(cko1_sels));

	clks[IMX6UL_CLK_CKO2_SEL]	  = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));

	clks[IMX6UL_CLK_CKO]		  = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));



	clks[IMX6UL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);

	clks[IMX6UL_CLK_LDB_DI0_DIV_7]	 = imx_clk_fixed_factor("ldb_di0_div_7",   "ldb_di0_sel", 1, 7);

	clks[IMX6UL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "qspi1_sel", 2, 7);
@@ -316,6 +327,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clks[IMX6UL_CLK_LCDIF_PRED]	= imx_clk_divider("lcdif_pred",	   "lcdif_pre_sel",	base + 0x38, 12, 3);

	clks[IMX6UL_CLK_CSI_PODF]       = imx_clk_divider("csi_podf",      "csi_sel",           base + 0x3c, 11, 3);



	clks[IMX6UL_CLK_CKO1_PODF]	= imx_clk_divider("cko1_podf",     "cko1_sel",          base + 0x60, 4,  3);

	clks[IMX6UL_CLK_CKO2_PODF]	= imx_clk_divider("cko2_podf",     "cko2_sel",          base + 0x60, 21, 3);



	clks[IMX6UL_CLK_ARM]		= imx_clk_busy_divider("arm",	    "pll1_sw",	base +	0x10, 0,  3,  base + 0x48, 16);

	clks[IMX6UL_CLK_MMDC_PODF]	= imx_clk_busy_divider("mmdc_podf", "periph2",	base +  0x14, 3,  3,  base + 0x48, 2);

	clks[IMX6UL_CLK_AXI_PODF]	= imx_clk_busy_divider("axi_podf",  "axi_sel",	base +  0x14, 16, 3,  base + 0x48, 0);
@@ -445,6 +459,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clks[IMX6UL_CLK_PWM6]		= imx_clk_gate2("pwm6",		"perclk",	 base +	0x80,	28);

	clks[IMX6UL_CLK_PWM7]		= imx_clk_gate2("pwm7",		"perclk",	 base + 0x80,	30);



	/* CCOSR */

	clks[IMX6UL_CLK_CKO1]		= imx_clk_gate("cko1",		"cko1_podf",	 base + 0x60,	7);

	clks[IMX6UL_CLK_CKO2]		= imx_clk_gate("cko2",		"cko2_podf",	 base + 0x60,	24);



	/* mask handshake of mmdc */

	writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);

drivers/clk/mediatek/Kconfig

+6 −0
Original line number Diff line number Diff line
@@ -60,6 +60,12 @@ config COMMON_CLK_MT2701_AUDSYS 
	---help---

	  This driver supports Mediatek MT2701 audsys clocks.



config COMMON_CLK_MT2701_G3DSYS

	bool "Clock driver for MediaTek MT2701 g3dsys"

	depends on COMMON_CLK_MT2701

	---help---

	  This driver supports MediaTek MT2701 g3dsys clocks.



config COMMON_CLK_MT2712

	bool "Clock driver for MediaTek MT2712"

	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

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