Merge branch 'v5.5/dt' into v5.5/drivers

Required Properties:

- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D,

		  "amlogic,g12a-audio-clkc" for G12A.

		  "amlogic,g12a-audio-clkc" for G12A,

		  "amlogic,sm1-audio-clkc" for S905X3.

- reg		: physical base address of the clock controller and length of

		  memory mapped region.

- clocks	: a list of phandle + clock-specifier pairs for the clocks listed

#define AUD_CLKID_TDM_SCLK_PAD0		160

#define AUD_CLKID_TDM_SCLK_PAD1		161

#define AUD_CLKID_TDM_SCLK_PAD2		162

#define AUD_CLKID_TOP			163

#define AUD_CLKID_TORAM			164

#define AUD_CLKID_EQDRC			165

#define AUD_CLKID_RESAMPLE_B		166

#define AUD_CLKID_TOVAD			167

#define AUD_CLKID_LOCKER		168

#define AUD_CLKID_SPDIFIN_LB		169

#define AUD_CLKID_FRDDR_D		170

#define AUD_CLKID_TODDR_D		171

#define AUD_CLKID_LOOPBACK_B		172

#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */

#define AUD_RESET_TOHDMITX	24

#define AUD_RESET_CLKTREE	25

/* SM1 added resets */

#define AUD_RESET_RESAMPLE_B	26

#define AUD_RESET_TOVAD		27

#define AUD_RESET_LOCKER	28

#define AUD_RESET_SPDIFIN_LB	29

#define AUD_RESET_FRATV		30

#define AUD_RESET_FRHDMIRX	31

#define AUD_RESET_FRDDR_D	32

#define AUD_RESET_TODDR_D	33

#define AUD_RESET_LOOPBACK_B	34

#define AUD_RESET_EARCTX	35

#define AUD_RESET_EARCRX	36

#define AUD_RESET_FRDDR_E	37

#define AUD_RESET_TODDR_E	38

#endif