Commit 90b171f6 authored by Neil Armstrong's avatar Neil Armstrong Committed by Jerome Brunet
Browse files

clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes 



When setting the 100MHz, 500MHz, 666MHz and 1GHz rate for CPU clocks,
CCF will use the SYS_PLL to handle these frequencies, but:
- using FIXED_PLL derived FCLK_DIV2/DIV3 clocks is more precise
- the Amlogic G12A/G12B/SM1 Suspend handling in firmware doesn't
  handle entering suspend using SYS_PLL for these frequencies

Adding CLK_MUX_ROUND_CLOSEST on all the muxes of the non-SYS_PLL
cpu clock tree helps CCF always selecting the FCLK_DIV2/DIV3 as source
for these frequencies.

Fixes: ffae8475 ("clk: meson: g12a: add notifiers to handle cpu clock change")
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 4a079643

drivers/clk/meson/g12a.c

+9 −0
Original line number Diff line number Diff line
@@ -343,6 +343,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = { 
		.offset = HHI_SYS_CPU_CLK_CNTL0,

		.mask = 0x3,

		.shift = 0,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu_clk_dyn0_sel",
@@ -409,6 +410,7 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = { 
		.offset = HHI_SYS_CPU_CLK_CNTL0,

		.mask = 0x1,

		.shift = 2,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu_clk_dyn0",
@@ -465,6 +467,7 @@ static struct clk_regmap g12a_cpu_clk_dyn = { 
		.offset = HHI_SYS_CPU_CLK_CNTL0,

		.mask = 0x1,

		.shift = 10,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu_clk_dyn",
@@ -484,6 +487,7 @@ static struct clk_regmap g12a_cpu_clk = { 
		.offset = HHI_SYS_CPU_CLK_CNTL0,

		.mask = 0x1,

		.shift = 11,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu_clk",
@@ -503,6 +507,7 @@ static struct clk_regmap g12b_cpu_clk = { 
		.offset = HHI_SYS_CPU_CLK_CNTL0,

		.mask = 0x1,

		.shift = 11,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu_clk",
@@ -522,6 +527,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = { 
		.offset = HHI_SYS_CPUB_CLK_CNTL,

		.mask = 0x3,

		.shift = 0,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpub_clk_dyn0_sel",
@@ -567,6 +573,7 @@ static struct clk_regmap g12b_cpub_clk_postmux0 = { 
		.offset = HHI_SYS_CPUB_CLK_CNTL,

		.mask = 0x1,

		.shift = 2,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpub_clk_dyn0",
@@ -644,6 +651,7 @@ static struct clk_regmap g12b_cpub_clk_dyn = { 
		.offset = HHI_SYS_CPUB_CLK_CNTL,

		.mask = 0x1,

		.shift = 10,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpub_clk_dyn",
@@ -663,6 +671,7 @@ static struct clk_regmap g12b_cpub_clk = { 
		.offset = HHI_SYS_CPUB_CLK_CNTL,

		.mask = 0x1,

		.shift = 11,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpub_clk",

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