Commit 44a69517 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-qcom-8998-resets' into clk-next 

  - Add resets and make Qualcomm MSM8998 GCC driver more functional

* clk-qcom-8998-resets:
  clk: qcom: Drop unused 8998 clock
  clk: qcom: Leave mmss noc on for 8998
  clk: qcom: Add missing msm8998 resets
  clk: qcom: gcc-msm8998: Add clkref clocks
  clk: qcom: gcc-msm8998: Disable halt check of UFS clocks
  clk: qcom: gcc-msm8998: Drop hmss_dvm and lpass_at
  clk: qcom: Enumerate remaining msm8998 resets
  clk: qcom: Add xo dummy clk on msm8998
  clk: qcom: Fix MSM8998 resets
parents 58c05c82 0f1c6ca8

drivers/clk/qcom/gcc-msm8998.c

+207 −64
Original line number Diff line number Diff line
@@ -117,6 +117,17 @@ static const char * const gcc_parent_names_5[] = { 
	"core_bi_pll_test_se",

};



static struct clk_fixed_factor xo = {

	.mult = 1,

	.div = 1,

	.hw.init = &(struct clk_init_data){

		.name = "xo",

		.parent_names = (const char *[]){ "xo_board" },

		.num_parents = 1,

		.ops = &clk_fixed_factor_ops,

	},

};



static struct pll_vco fabia_vco[] = {

	{ 250000000, 2000000000, 0 },

	{ 125000000, 1000000000, 1 },
@@ -1964,19 +1975,6 @@ static struct clk_branch gcc_hmss_at_clk = { 
	},

};



static struct clk_branch gcc_hmss_dvm_bus_clk = {

	.halt_reg = 0x4808c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x4808c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_hmss_dvm_bus_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_hmss_rbcpr_clk = {

	.halt_reg = 0x48008,

	.halt_check = BRANCH_HALT,
@@ -2007,32 +2005,6 @@ static struct clk_branch gcc_hmss_trig_clk = { 
	},

};



static struct clk_branch gcc_lpass_at_clk = {

	.halt_reg = 0x47020,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x47020,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_lpass_at_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_lpass_trig_clk = {

	.halt_reg = 0x4701c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x4701c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_lpass_trig_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {

	.halt_reg = 0x9004,

	.halt_check = BRANCH_HALT,
@@ -2042,6 +2014,12 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { 
		.hw.init = &(struct clk_init_data){

			.name = "gcc_mmss_noc_cfg_ahb_clk",

			.ops = &clk_branch2_ops,

			/*

			 * Any access to mmss depends on this clock.

			 * Gating this clock has been shown to crash the system

			 * when mmssnoc_axi_rpm_clk is inited in rpmcc.

			 */

			.flags = CLK_IS_CRITICAL,

		},

	},

};
@@ -2401,7 +2379,7 @@ static struct clk_branch gcc_ufs_phy_aux_clk = { 


static struct clk_branch gcc_ufs_rx_symbol_0_clk = {

	.halt_reg = 0x75014,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x75014,

		.enable_mask = BIT(0),
@@ -2414,7 +2392,7 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 


static struct clk_branch gcc_ufs_rx_symbol_1_clk = {

	.halt_reg = 0x7605c,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x7605c,

		.enable_mask = BIT(0),
@@ -2427,7 +2405,7 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 


static struct clk_branch gcc_ufs_tx_symbol_0_clk = {

	.halt_reg = 0x75010,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x75010,

		.enable_mask = BIT(0),
@@ -2541,6 +2519,76 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 
	},

};



static struct clk_branch gcc_hdmi_clkref_clk = {

	.halt_reg = 0x88000,

	.clkr = {

		.enable_reg = 0x88000,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_hdmi_clkref_clk",

			.parent_names = (const char *[]){ "xo" },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_ufs_clkref_clk = {

	.halt_reg = 0x88004,

	.clkr = {

		.enable_reg = 0x88004,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_clkref_clk",

			.parent_names = (const char *[]){ "xo" },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_usb3_clkref_clk = {

	.halt_reg = 0x88008,

	.clkr = {

		.enable_reg = 0x88008,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_usb3_clkref_clk",

			.parent_names = (const char *[]){ "xo" },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_pcie_clkref_clk = {

	.halt_reg = 0x8800c,

	.clkr = {

		.enable_reg = 0x8800c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_clkref_clk",

			.parent_names = (const char *[]){ "xo" },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_rx1_usb2_clkref_clk = {

	.halt_reg = 0x88014,

	.clkr = {

		.enable_reg = 0x88014,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_rx1_usb2_clkref_clk",

			.parent_names = (const char *[]){ "xo" },

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct gdsc pcie_0_gdsc = {

	.gdscr = 0x6b004,

	.gds_hw_ctrl = 0x0,
@@ -2653,11 +2701,8 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { 
	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,

	[GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,

	[GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,

	[GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,

	[GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,

	[GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,

	[GCC_LPASS_AT_CLK] = &gcc_lpass_at_clk.clkr,

	[GCC_LPASS_TRIG_CLK] = &gcc_lpass_trig_clk.clkr,

	[GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,

	[GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,

	[GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
@@ -2733,6 +2778,11 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { 
	[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,

	[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,

	[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,

	[GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,

	[GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,

	[GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,

	[GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,

	[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,

};



static struct gdsc *gcc_msm8998_gdscs[] = {
@@ -2742,25 +2792,114 @@ static struct gdsc *gcc_msm8998_gdscs[] = { 
};



static const struct qcom_reset_map gcc_msm8998_resets[] = {

	[GCC_BLSP1_QUP1_BCR] = { 0x102400 },

	[GCC_BLSP1_QUP2_BCR] = { 0x110592 },

	[GCC_BLSP1_QUP3_BCR] = { 0x118784 },

	[GCC_BLSP1_QUP4_BCR] = { 0x126976 },

	[GCC_BLSP1_QUP5_BCR] = { 0x135168 },

	[GCC_BLSP1_QUP6_BCR] = { 0x143360 },

	[GCC_BLSP2_QUP1_BCR] = { 0x155648 },

	[GCC_BLSP2_QUP2_BCR] = { 0x163840 },

	[GCC_BLSP2_QUP3_BCR] = { 0x172032 },

	[GCC_BLSP2_QUP4_BCR] = { 0x180224 },

	[GCC_BLSP2_QUP5_BCR] = { 0x188416 },

	[GCC_BLSP2_QUP6_BCR] = { 0x196608 },

	[GCC_PCIE_0_BCR] = { 0x438272 },

	[GCC_PDM_BCR] = { 0x208896 },

	[GCC_SDCC2_BCR] = { 0x81920 },

	[GCC_SDCC4_BCR] = { 0x90112 },

	[GCC_TSIF_BCR] = { 0x221184 },

	[GCC_UFS_BCR] = { 0x479232 },

	[GCC_USB_30_BCR] = { 0x61440 },

	[GCC_BLSP1_QUP1_BCR] = { 0x19000 },

	[GCC_BLSP1_QUP2_BCR] = { 0x1b000 },

	[GCC_BLSP1_QUP3_BCR] = { 0x1d000 },

	[GCC_BLSP1_QUP4_BCR] = { 0x1f000 },

	[GCC_BLSP1_QUP5_BCR] = { 0x21000 },

	[GCC_BLSP1_QUP6_BCR] = { 0x23000 },

	[GCC_BLSP2_QUP1_BCR] = { 0x26000 },

	[GCC_BLSP2_QUP2_BCR] = { 0x28000 },

	[GCC_BLSP2_QUP3_BCR] = { 0x2a000 },

	[GCC_BLSP2_QUP4_BCR] = { 0x2c000 },

	[GCC_BLSP2_QUP5_BCR] = { 0x2e000 },

	[GCC_BLSP2_QUP6_BCR] = { 0x30000 },

	[GCC_PCIE_0_BCR] = { 0x6b000 },

	[GCC_PDM_BCR] = { 0x33000 },

	[GCC_SDCC2_BCR] = { 0x14000 },

	[GCC_SDCC4_BCR] = { 0x16000 },

	[GCC_TSIF_BCR] = { 0x36000 },

	[GCC_UFS_BCR] = { 0x75000 },

	[GCC_USB_30_BCR] = { 0xf000 },

	[GCC_SYSTEM_NOC_BCR] = { 0x4000 },

	[GCC_CONFIG_NOC_BCR] = { 0x5000 },

	[GCC_AHB2PHY_EAST_BCR] = { 0x7000 },

	[GCC_IMEM_BCR] = { 0x8000 },

	[GCC_PIMEM_BCR] = { 0xa000 },

	[GCC_MMSS_BCR] = { 0xb000 },

	[GCC_QDSS_BCR] = { 0xc000 },

	[GCC_WCSS_BCR] = { 0x11000 },

	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },

	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },

	[GCC_BLSP1_BCR] = { 0x17000 },

	[GCC_BLSP1_UART1_BCR] = { 0x1a000 },

	[GCC_BLSP1_UART2_BCR] = { 0x1c000 },

	[GCC_BLSP1_UART3_BCR] = { 0x1e000 },

	[GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 },

	[GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 },

	[GCC_BLSP2_BCR] = { 0x25000 },

	[GCC_BLSP2_UART1_BCR] = { 0x27000 },

	[GCC_BLSP2_UART2_BCR] = { 0x29000 },

	[GCC_BLSP2_UART3_BCR] = { 0x2b000 },

	[GCC_SRAM_SENSOR_BCR] = { 0x2d000 },

	[GCC_PRNG_BCR] = { 0x34000 },

	[GCC_TSIF_0_RESET] = { 0x36024 },

	[GCC_TSIF_1_RESET] = { 0x36028 },

	[GCC_TCSR_BCR] = { 0x37000 },

	[GCC_BOOT_ROM_BCR] = { 0x38000 },

	[GCC_MSG_RAM_BCR] = { 0x39000 },

	[GCC_TLMM_BCR] = { 0x3a000 },

	[GCC_MPM_BCR] = { 0x3b000 },

	[GCC_SEC_CTRL_BCR] = { 0x3d000 },

	[GCC_SPMI_BCR] = { 0x3f000 },

	[GCC_SPDM_BCR] = { 0x40000 },

	[GCC_CE1_BCR] = { 0x41000 },

	[GCC_BIMC_BCR] = { 0x44000 },

	[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },

	[GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 },

	[GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 },

	[GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 },

	[GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },

	[GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 },

	[GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c },

	[GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },

	[GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },

	[GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },

	[GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },

	[GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },

	[GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },

	[GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },

	[GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },

	[GCC_APB2JTAG_BCR] = { 0x4c000 },

	[GCC_RBCPR_CX_BCR] = { 0x4e000 },

	[GCC_RBCPR_MX_BCR] = { 0x4f000 },

	[GCC_USB3_PHY_BCR] = { 0x50020 },

	[GCC_USB3PHY_PHY_BCR] = { 0x50024 },

	[GCC_USB3_DP_PHY_BCR] = { 0x50028 },

	[GCC_SSC_BCR] = { 0x63000 },

	[GCC_SSC_RESET] = { 0x63020 },

	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },

	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },

	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },

	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },

	[GCC_PCIE_PHY_BCR] = { 0x6f000 },

	[GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c },

	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 },

	[GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },

	[GCC_GPU_BCR] = { 0x71000 },

	[GCC_SPSS_BCR] = { 0x72000 },

	[GCC_OBT_ODT_BCR] = { 0x73000 },

	[GCC_VS_BCR] = { 0x7a000 },

	[GCC_MSS_VS_RESET] = { 0x7a100 },

	[GCC_GPU_VS_RESET] = { 0x7a104 },

	[GCC_APC0_VS_RESET] = { 0x7a108 },

	[GCC_APC1_VS_RESET] = { 0x7a10c },

	[GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },

	[GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },

	[GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 },

	[GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 },

	[GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 },

	[GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 },

	[GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 },

	[GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 },

	[GCC_AGGRE1_NOC_BCR] = { 0x82000 },

	[GCC_AGGRE2_NOC_BCR] = { 0x83000 },

	[GCC_DCC_BCR] = { 0x84000 },

	[GCC_QREFS_VBG_CAL_BCR] = { 0x88028 },

	[GCC_IPA_BCR] = { 0x89000 },

	[GCC_GLM_BCR] = { 0x8b000 },

	[GCC_SKL_BCR] = { 0x8c000 },

	[GCC_MSMPU_BCR] = { 0x8d000 },

};



static const struct regmap_config gcc_msm8998_regmap_config = {
@@ -2798,6 +2937,10 @@ static int gcc_msm8998_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	ret = devm_clk_hw_register(&pdev->dev, &xo.hw);

	if (ret)

		return ret;



	return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);

}

include/dt-bindings/clock/qcom,gcc-msm8998.h

+94 −0
Original line number Diff line number Diff line
@@ -180,6 +180,11 @@ 
#define USB30_MASTER_CLK_SRC					163

#define USB30_MOCK_UTMI_CLK_SRC					164

#define USB3_PHY_AUX_CLK_SRC					165

#define GCC_USB3_CLKREF_CLK					166

#define GCC_HDMI_CLKREF_CLK					167

#define GCC_UFS_CLKREF_CLK					168

#define GCC_PCIE_CLKREF_CLK					169

#define GCC_RX1_USB2_CLKREF_CLK					170



#define PCIE_0_GDSC						0

#define UFS_GDSC						1
@@ -204,5 +209,94 @@ 
#define GCC_TSIF_BCR						16

#define GCC_UFS_BCR						17

#define GCC_USB_30_BCR						18

#define GCC_SYSTEM_NOC_BCR					19

#define GCC_CONFIG_NOC_BCR					20

#define GCC_AHB2PHY_EAST_BCR					21

#define GCC_IMEM_BCR						22

#define GCC_PIMEM_BCR						23

#define GCC_MMSS_BCR						24

#define GCC_QDSS_BCR						25

#define GCC_WCSS_BCR						26

#define GCC_BLSP1_BCR						27

#define GCC_BLSP1_UART1_BCR					28

#define GCC_BLSP1_UART2_BCR					29

#define GCC_BLSP1_UART3_BCR					30

#define GCC_CM_PHY_REFGEN1_BCR					31

#define GCC_CM_PHY_REFGEN2_BCR					32

#define GCC_BLSP2_BCR						33

#define GCC_BLSP2_UART1_BCR					34

#define GCC_BLSP2_UART2_BCR					35

#define GCC_BLSP2_UART3_BCR					36

#define GCC_SRAM_SENSOR_BCR					37

#define GCC_PRNG_BCR						38

#define GCC_TSIF_0_RESET					39

#define GCC_TSIF_1_RESET					40

#define GCC_TCSR_BCR						41

#define GCC_BOOT_ROM_BCR					42

#define GCC_MSG_RAM_BCR						43

#define GCC_TLMM_BCR						44

#define GCC_MPM_BCR						45

#define GCC_SEC_CTRL_BCR					46

#define GCC_SPMI_BCR						47

#define GCC_SPDM_BCR						48

#define GCC_CE1_BCR						49

#define GCC_BIMC_BCR						50

#define GCC_SNOC_BUS_TIMEOUT0_BCR				51

#define GCC_SNOC_BUS_TIMEOUT1_BCR				52

#define GCC_SNOC_BUS_TIMEOUT3_BCR				53

#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR				54

#define GCC_PNOC_BUS_TIMEOUT0_BCR				55

#define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR			56

#define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR			57

#define GCC_CNOC_BUS_TIMEOUT0_BCR				58

#define GCC_CNOC_BUS_TIMEOUT1_BCR				59

#define GCC_CNOC_BUS_TIMEOUT2_BCR				60

#define GCC_CNOC_BUS_TIMEOUT3_BCR				61

#define GCC_CNOC_BUS_TIMEOUT4_BCR				62

#define GCC_CNOC_BUS_TIMEOUT5_BCR				63

#define GCC_CNOC_BUS_TIMEOUT6_BCR				64

#define GCC_CNOC_BUS_TIMEOUT7_BCR				65

#define GCC_APB2JTAG_BCR					66

#define GCC_RBCPR_CX_BCR					67

#define GCC_RBCPR_MX_BCR					68

#define GCC_USB3_PHY_BCR					69

#define GCC_USB3PHY_PHY_BCR					70

#define GCC_USB3_DP_PHY_BCR					71

#define GCC_SSC_BCR						72

#define GCC_SSC_RESET						73

#define GCC_USB_PHY_CFG_AHB2PHY_BCR				74

#define GCC_PCIE_0_LINK_DOWN_BCR				75

#define GCC_PCIE_0_PHY_BCR					76

#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				77

#define GCC_PCIE_PHY_BCR					78

#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR				79

#define GCC_PCIE_PHY_CFG_AHB_BCR				80

#define GCC_PCIE_PHY_COM_BCR					81

#define GCC_GPU_BCR						82

#define GCC_SPSS_BCR						83

#define GCC_OBT_ODT_BCR						84

#define GCC_VS_BCR						85

#define GCC_MSS_VS_RESET					86

#define GCC_GPU_VS_RESET					87

#define GCC_APC0_VS_RESET					88

#define GCC_APC1_VS_RESET					89

#define GCC_CNOC_BUS_TIMEOUT8_BCR				90

#define GCC_CNOC_BUS_TIMEOUT9_BCR				91

#define GCC_CNOC_BUS_TIMEOUT10_BCR				92

#define GCC_CNOC_BUS_TIMEOUT11_BCR				93

#define GCC_CNOC_BUS_TIMEOUT12_BCR				94

#define GCC_CNOC_BUS_TIMEOUT13_BCR				95

#define GCC_CNOC_BUS_TIMEOUT14_BCR				96

#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR				97

#define GCC_AGGRE1_NOC_BCR					98

#define GCC_AGGRE2_NOC_BCR					99

#define GCC_DCC_BCR						100

#define GCC_QREFS_VBG_CAL_BCR					101

#define GCC_IPA_BCR						102

#define GCC_GLM_BCR						103

#define GCC_SKL_BCR						104

#define GCC_MSMPU_BCR						105

#define GCC_QUSB2PHY_PRIM_BCR					106

#define GCC_QUSB2PHY_SEC_BCR					107



#endif

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