Commit 442489c2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'timers-core-2020-08-04' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull timer updates from Thomas Gleixner:
 "Time, timers and related driver updates:

   - Prevent unnecessary timer softirq invocations by extending the
     tracking of the next expiring timer in the timer wheel beyond the
     existing NOHZ functionality.

     The tracking overhead at enqueue time is within the noise, but on
     sensitive workloads the avoidance of the soft interrupt invocation
     is a measurable improvement.

   - The obligatory new clocksource driver for Ingenic X100 OST

   - The usual fixes, improvements, cleanups and extensions for newer
     chip variants all over the driver space"

* tag 'timers-core-2020-08-04' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (28 commits)
  timers: Recalculate next timer interrupt only when necessary
  clocksource/drivers/ingenic: Add support for the Ingenic X1000 OST.
  dt-bindings: timer: Add Ingenic X1000 OST bindings.
  clocksource/drivers: Replace HTTP links with HTTPS ones
  clocksource/drivers/nomadik-mtu: Handle 32kHz clock
  clocksource/drivers/sh_cmt: Use "kHz" for kilohertz
  clocksource/drivers/imx: Add support for i.MX TPM driver with ARM64
  clocksource/drivers/ingenic: Add high resolution timer support for SMP/SMT.
  timers: Lower base clock forwarding threshold
  timers: Remove must_forward_clk
  timers: Spare timer softirq until next expiry
  timers: Expand clk forward logic beyond nohz
  timers: Reuse next expiry cache after nohz exit
  timers: Always keep track of next expiry
  timers: Optimize _next_timer_interrupt() level iteration
  timers: Add comments about calc_index() ceiling work
  timers: Move trigger_dyntick_cpu() to enqueue_timer()
  timers: Use only bucket expiry for base->next_expiry value
  timers: Preserve higher bits of expiration on index calculation
  clocksource/drivers/timer-atmel-tcb: Add sama5d2 support
  ...
parents f8b036a7 31cd0e11

Documentation/devicetree/bindings/mfd/atmel-tcb.txt

deleted100644 → 0
+0 −56
Original line number Diff line number Diff line 
* Device tree bindings for Atmel Timer Counter Blocks

- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".

  <chip> can be "at91rm9200" or "at91sam9x5"

- reg: Should contain registers location and length

- #address-cells: has to be 1

- #size-cells: has to be 0

- interrupts: Should contain all interrupts for the TC block

  Note that you can specify several interrupt cells if the TC

  block has one interrupt per channel.

- clock-names: tuple listing input clock names.

	Required elements: "t0_clk", "slow_clk"

	Optional elements: "t1_clk", "t2_clk"

- clocks: phandles to input clocks.



The TCB can expose multiple subdevices:

 * a timer

   - compatible: Should be "atmel,tcb-timer"

   - reg: Should contain the TCB channels to be used. If the

     counter width is 16 bits (at91rm9200-tcb), two consecutive

     channels are needed. Else, only one channel will be used.



Examples:



One interrupt per TC block:

	tcb0: timer@fff7c000 {

		compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xfff7c000 0x100>;

		interrupts = <18 4>;

		clocks = <&tcb0_clk>, <&clk32k>;

		clock-names = "t0_clk", "slow_clk";



		timer@0 {

			compatible = "atmel,tcb-timer";

			reg = <0>, <1>;

		};



		timer@2 {

			compatible = "atmel,tcb-timer";

			reg = <2>;

		};

	};



One interrupt per TC channel in a TC block:

	tcb1: timer@fffdc000 {

		compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xfffdc000 0x100>;

		interrupts = <26 4>, <27 4>, <28 4>;

		clocks = <&tcb1_clk>, <&clk32k>;

		clock-names = "t0_clk", "slow_clk";

	};

Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml

0 → 100644
+155 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Atmel Timer Counter Block



maintainers:

  - Alexandre Belloni <alexandre.belloni@bootlin.com>



description: |

  The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each

  timer has three channels with two counters each.



properties:

  compatible:

    items:

      - enum:

          - atmel,at91rm9200-tcb

          - atmel,at91sam9x5-tcb

          - atmel,sama5d2-tcb

      - const: simple-mfd

      - const: syscon



  reg:

    maxItems: 1



  interrupts:

    description:

      List of interrupts. One interrupt per TCB channel if available or one

      interrupt for the TC block

    minItems: 1

    maxItems: 3



  clock-names:

    description:

      List of clock names. Always includes t0_clk and slow clk. Also includes

      t1_clk and t2_clk if a clock per channel is available.

    minItems: 2

    maxItems: 4



  clocks:

    minItems: 2

    maxItems: 4



  '#address-cells':

    const: 1



  '#size-cells':

    const: 0



patternProperties:

  "^timer@[0-2]$":

    description: The timer block channels that are used as timers.

    type: object

    properties:

      compatible:

        const: atmel,tcb-timer

      reg:

        description:

          List of channels to use for this particular timer.

        minItems: 1

        maxItems: 3



    required:

      - compatible

      - reg



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: atmel,sama5d2-tcb

    then:

      properties:

        clocks:

          minItems: 3

          maxItems: 3

        clock-names:

          items:

            - const: t0_clk

            - const: gclk

            - const: slow_clk

    else:

      properties:

        clocks:

          minItems: 2

          maxItems: 4

        clock-names:

          oneOf:

            - items:

              - const: t0_clk

              - const: slow_clk

            - items:

              - const: t0_clk

              - const: t1_clk

              - const: t2_clk

              - const: slow_clk



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - '#address-cells'

  - '#size-cells'



additionalProperties: false



examples:

  - |

    /* One interrupt per TC block: */

        tcb0: timer@fff7c000 {

                compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";

                #address-cells = <1>;

                #size-cells = <0>;

                reg = <0xfff7c000 0x100>;

                interrupts = <18 4>;

                clocks = <&tcb0_clk>, <&clk32k>;

                clock-names = "t0_clk", "slow_clk";



                timer@0 {

                        compatible = "atmel,tcb-timer";

                        reg = <0>, <1>;

                };



                timer@2 {

                        compatible = "atmel,tcb-timer";

                        reg = <2>;

                };

        };



    /* One interrupt per TC channel in a TC block: */

        tcb1: timer@fffdc000 {

                compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";

                #address-cells = <1>;

                #size-cells = <0>;

                reg = <0xfffdc000 0x100>;

                interrupts = <26 4>, <27 4>, <28 4>;

                clocks = <&tcb1_clk>, <&clk32k>;

                clock-names = "t0_clk", "slow_clk";



                timer@0 {

                        compatible = "atmel,tcb-timer";

                        reg = <0>;

                };



                timer@1 {

                        compatible = "atmel,tcb-timer";

                        reg = <1>;

                };

        };

Documentation/devicetree/bindings/timer/ingenic,sysost.yaml

0 → 100644
+63 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/timer/ingenic,sysost.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Bindings for SYSOST in Ingenic XBurst family SoCs



maintainers:

  - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>



description:

  The SYSOST in an Ingenic SoC provides one 64bit timer for clocksource

  and one or more 32bit timers for clockevent.



properties:

  "#clock-cells":

    const: 1



  compatible:

    enum:

      - ingenic,x1000-ost

      - ingenic,x2000-ost



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    const: ost



  interrupts:

    maxItems: 1



required:

  - "#clock-cells"

  - compatible

  - reg

  - clocks

  - clock-names

  - interrupts



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/x1000-cgu.h>



    ost: timer@12000000 {

        compatible = "ingenic,x1000-ost";

        reg = <0x12000000 0x3c>;



        #clock-cells = <1>;



        clocks = <&cgu X1000_CLK_OST>;

        clock-names = "ost";



        interrupt-parent = <&cpuintc>;

        interrupts = <3>;

    };

...

Documentation/devicetree/bindings/timer/ti,keystone-timer.txt

+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ It is global timer is a free running up-counter and can generate interrupt 
when the counter reaches preset counter values.



Documentation:

http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf

https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf



Required properties:

arch/arm/boot/dts/sama5d2.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -375,23 +375,23 @@ 
			};



			tcb0: timer@f800c000 {

				compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";

				compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";

				#address-cells = <1>;

				#size-cells = <0>;

				reg = <0xf800c000 0x100>;

				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>;

				clock-names = "t0_clk", "slow_clk";

				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>;

				clock-names = "t0_clk", "gclk", "slow_clk";

			};



			tcb1: timer@f8010000 {

				compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";

				compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";

				#address-cells = <1>;

				#size-cells = <0>;

				reg = <0xf8010000 0x100>;

				interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;

				clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>;

				clock-names = "t0_clk", "slow_clk";

				clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>;

				clock-names = "t0_clk", "gclk", "slow_clk";

			};



			hsmc: hsmc@f8014000 {

CRA Git | Maintained and supported by SUSTech CRA and CCSE