Commit 43f01da0 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS/OCTEON/ata: Convert pata_octeon_cf.c to use device tree. 



The patch needs to eliminate the definition of OCTEON_IRQ_BOOTDMA so
that the device tree code can map the interrupt, so in order to not
temporarily break things, we do a single patch to both the interrupt
registration code and the pata_octeon_cf driver.

Also rolled in is a conversion to use hrtimers and corrections to the
timing calculations.

Acked-by: default avatarJeff Garzik <jgarzik@redhat.com>
Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
parent f772cdb2

arch/mips/cavium-octeon/octeon-irq.c

+0 −1
Original line number Diff line number Diff line
@@ -1266,7 +1266,6 @@ static void __init octeon_irq_init_ciu(void) 
		octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52);



	octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56);

	octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_BOOTDMA, 0, 63);



	/* CIU_1 */

	for (i = 0; i < 16; i++)

arch/mips/cavium-octeon/octeon-platform.c

+0 −102
Original line number Diff line number Diff line
@@ -24,108 +24,6 @@ 
#include <asm/octeon/cvmx-helper.h>

#include <asm/octeon/cvmx-helper-board.h>



static struct octeon_cf_data octeon_cf_data;



static int __init octeon_cf_device_init(void)

{

	union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;

	unsigned long base_ptr, region_base, region_size;

	struct platform_device *pd;

	struct resource cf_resources[3];

	unsigned int num_resources;

	int i;

	int ret = 0;



	/* Setup octeon-cf platform device if present. */

	base_ptr = 0;

	if (octeon_bootinfo->major_version == 1

		&& octeon_bootinfo->minor_version >= 1) {

		if (octeon_bootinfo->compact_flash_common_base_addr)

			base_ptr =

				octeon_bootinfo->compact_flash_common_base_addr;

	} else {

		base_ptr = 0x1d000800;

	}



	if (!base_ptr)

		return ret;



	/* Find CS0 region. */

	for (i = 0; i < 8; i++) {

		mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));

		region_base = mio_boot_reg_cfg.s.base << 16;

		region_size = (mio_boot_reg_cfg.s.size + 1) << 16;

		if (mio_boot_reg_cfg.s.en && base_ptr >= region_base

		    && base_ptr < region_base + region_size)

			break;

	}

	if (i >= 7) {

		/* i and i + 1 are CS0 and CS1, both must be less than 8. */

		goto out;

	}

	octeon_cf_data.base_region = i;

	octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;

	octeon_cf_data.base_region_bias = base_ptr - region_base;

	memset(cf_resources, 0, sizeof(cf_resources));

	num_resources = 0;

	cf_resources[num_resources].flags	= IORESOURCE_MEM;

	cf_resources[num_resources].start	= region_base;

	cf_resources[num_resources].end	= region_base + region_size - 1;

	num_resources++;





	if (!(base_ptr & 0xfffful)) {

		/*

		 * Boot loader signals availability of DMA (true_ide

		 * mode) by setting low order bits of base_ptr to

		 * zero.

		 */



		/* Assume that CS1 immediately follows. */

		mio_boot_reg_cfg.u64 =

			cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));

		region_base = mio_boot_reg_cfg.s.base << 16;

		region_size = (mio_boot_reg_cfg.s.size + 1) << 16;

		if (!mio_boot_reg_cfg.s.en)

			goto out;



		cf_resources[num_resources].flags	= IORESOURCE_MEM;

		cf_resources[num_resources].start	= region_base;

		cf_resources[num_resources].end	= region_base + region_size - 1;

		num_resources++;



		octeon_cf_data.dma_engine = 0;

		cf_resources[num_resources].flags	= IORESOURCE_IRQ;

		cf_resources[num_resources].start	= OCTEON_IRQ_BOOTDMA;

		cf_resources[num_resources].end	= OCTEON_IRQ_BOOTDMA;

		num_resources++;

	} else {

		octeon_cf_data.dma_engine = -1;

	}



	pd = platform_device_alloc("pata_octeon_cf", -1);

	if (!pd) {

		ret = -ENOMEM;

		goto out;

	}

	pd->dev.platform_data = &octeon_cf_data;



	ret = platform_device_add_resources(pd, cf_resources, num_resources);

	if (ret)

		goto fail;



	ret = platform_device_add(pd);

	if (ret)

		goto fail;



	return ret;

fail:

	platform_device_put(pd);

out:

	return ret;

}

device_initcall(octeon_cf_device_init);



/* Octeon Random Number Generator.  */

static int __init octeon_rng_device_init(void)

{

arch/mips/include/asm/mach-cavium-octeon/irq.h

+0 −1
Original line number Diff line number Diff line
@@ -42,7 +42,6 @@ enum octeon_irq { 
	OCTEON_IRQ_TIMER3,

	OCTEON_IRQ_USB0,

	OCTEON_IRQ_USB1,

	OCTEON_IRQ_BOOTDMA,

#ifndef CONFIG_PCI_MSI

	OCTEON_IRQ_LAST = 127

#endif

arch/mips/include/asm/octeon/octeon.h

+0 −7
Original line number Diff line number Diff line
@@ -209,13 +209,6 @@ union octeon_cvmemctl { 
	} s;

};



struct octeon_cf_data {

	unsigned long	base_region_bias;

	unsigned int	base_region;	/* The chip select region used by CF */

	int		is16bit;	/* 0 - 8bit, !0 - 16bit */

	int		dma_engine;	/* -1 for no DMA */

};



extern void octeon_write_lcd(const char *s);

extern void octeon_check_cpu_bist(void);

extern int octeon_get_boot_debug_flag(void);

drivers/ata/pata_octeon_cf.c

+284 −135

File changed.

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