Commit 40a6bbf5 authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

tools x86 headers: Update cpufeatures.h headers copies 



To pick the changes from:

  5866e920 ("x86/cpu: Add hardware-enforced cache coherency as a CPUID feature")
  ff4f8281 ("x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions")
  360e7c5c ("x86/cpufeatures: Add SEV-ES CPU feature")
  18ec63fa ("x86/cpufeatures: Enumerate TSX suspend load address tracking instructions")
  e48cb1a3 ("x86/resctrl: Enumerate per-thread MBA controls")

Which don't cause any changes in tooling, just addresses these build
warnings:

  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
  diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
  Warning: Kernel ABI header at 'tools/arch/x86/include/asm/disabled-features.h' differs from latest version at 'arch/x86/include/asm/disabled-features.h'
  diff -u tools/arch/x86/include/asm/disabled-features.h arch/x86/include/asm/disabled-features.h

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Cc: Kyung Min Park <kyung.min.park@intel.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent d0448d6a

tools/arch/x86/include/asm/cpufeatures.h

+5 −1
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ 
#define X86_FEATURE_SYSCALL32		( 3*32+14) /* "" syscall in IA32 userspace */

#define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */

#define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */

/* free					( 3*32+17) */

#define X86_FEATURE_SME_COHERENT	( 3*32+17) /* "" AMD hardware-enforced cache coherency */

#define X86_FEATURE_LFENCE_RDTSC	( 3*32+18) /* "" LFENCE synchronizes RDTSC */

#define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */

#define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */
@@ -236,6 +236,7 @@ 
#define X86_FEATURE_EPT_AD		( 8*32+17) /* Intel Extended Page Table access-dirty bit */

#define X86_FEATURE_VMCALL		( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */

#define X86_FEATURE_VMW_VMMCALL		( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */

#define X86_FEATURE_SEV_ES		( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */



/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */

#define X86_FEATURE_FSGSBASE		( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
@@ -288,6 +289,7 @@ 
#define X86_FEATURE_FENCE_SWAPGS_USER	(11*32+ 4) /* "" LFENCE in user entry SWAPGS path */

#define X86_FEATURE_FENCE_SWAPGS_KERNEL	(11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */

#define X86_FEATURE_SPLIT_LOCK_DETECT	(11*32+ 6) /* #AC for split lock */

#define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */



/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
@@ -353,6 +355,7 @@ 
#define X86_FEATURE_CLDEMOTE		(16*32+25) /* CLDEMOTE instruction */

#define X86_FEATURE_MOVDIRI		(16*32+27) /* MOVDIRI instruction */

#define X86_FEATURE_MOVDIR64B		(16*32+28) /* MOVDIR64B instruction */

#define X86_FEATURE_ENQCMD		(16*32+29) /* ENQCMD and ENQCMDS instructions */



/* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */

#define X86_FEATURE_OVERFLOW_RECOV	(17*32+ 0) /* MCA overflow recovery support */
@@ -368,6 +371,7 @@ 
#define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */

#define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */

#define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */

#define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */

#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

tools/arch/x86/include/asm/disabled-features.h

+8 −1
Original line number Diff line number Diff line
@@ -56,6 +56,12 @@ 
# define DISABLE_PTI		(1 << (X86_FEATURE_PTI & 31))

#endif



#ifdef CONFIG_IOMMU_SUPPORT

# define DISABLE_ENQCMD	0

#else

# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31))

#endif



/*

 * Make sure to add features to the correct mask

 */
@@ -75,7 +81,8 @@ 
#define DISABLED_MASK13	0

#define DISABLED_MASK14	0

#define DISABLED_MASK15	0

#define DISABLED_MASK16	(DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP)

#define DISABLED_MASK16	(DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP| \

			 DISABLE_ENQCMD)

#define DISABLED_MASK17	0

#define DISABLED_MASK18	0

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)

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