Commit 5866e920 authored by Krish Sadhukhan's avatar Krish Sadhukhan Committed by Borislav Petkov
Browse files

x86/cpu: Add hardware-enforced cache coherency as a CPUID feature 



In some hardware implementations, coherency between the encrypted and
unencrypted mappings of the same physical page is enforced. In such a system,
it is not required for software to flush the page from all CPU caches in the
system prior to changing the value of the C-bit for a page. This hardware-
enforced cache coherency is indicated by EAX[10] in CPUID leaf 0x8000001f.

 [ bp: Use one of the free slots in word 3. ]

Suggested-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: default avatarKrish Sadhukhan <krish.sadhukhan@oracle.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200917212038.5090-2-krish.sadhukhan@oracle.com
parent 33b4711d

arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ 
#define X86_FEATURE_SYSCALL32		( 3*32+14) /* "" syscall in IA32 userspace */

#define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */

#define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */

/* free					( 3*32+17) */

#define X86_FEATURE_SME_COHERENT	( 3*32+17) /* "" AMD hardware-enforced cache coherency */

#define X86_FEATURE_LFENCE_RDTSC	( 3*32+18) /* "" LFENCE synchronizes RDTSC */

#define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */

#define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */

arch/x86/kernel/cpu/scattered.c

+1 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ static const struct cpuid_bit cpuid_bits[] = { 
	{ X86_FEATURE_MBA,		CPUID_EBX,  6, 0x80000008, 0 },

	{ X86_FEATURE_SME,		CPUID_EAX,  0, 0x8000001f, 0 },

	{ X86_FEATURE_SEV,		CPUID_EAX,  1, 0x8000001f, 0 },

	{ X86_FEATURE_SME_COHERENT,	CPUID_EAX, 10, 0x8000001f, 0 },

	{ 0, 0, 0, 0, 0 }

};

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