Commit 3f31dedb authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.10-2020-10-21' of... 

Merge tag 'amd-drm-fixes-5.10-2020-10-21' of git://people.freedesktop.org/~agd5f/linux

 into drm-next

amd-drm-fixes-5.10-2020-10-21:

amdgpu:
- Sienna Cichlid fixes
- MST manager resource leak fix
- GPU reset fix

amdkfd:
- Luxmark fix for Navi1x

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201022040322.4183-1-alexander.deucher@amd.com
parents fea456d8 687e79c0

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −1
Original line number Diff line number Diff line
@@ -4625,7 +4625,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 
retry:	/* Rest of adevs pre asic reset from XGMI hive. */

	list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {

		r = amdgpu_device_pre_asic_reset(tmp_adev,

						 NULL,

						 (tmp_adev == adev) ? job : NULL,

						 &need_full_reset);

		/*TODO Should we stop ?*/

		if (r) {

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+8 −1
Original line number Diff line number Diff line
@@ -208,7 +208,8 @@ static int psp_sw_fini(void *handle) 
		adev->psp.ta_fw = NULL;

	}



	if (adev->asic_type == CHIP_NAVI10)

	if (adev->asic_type == CHIP_NAVI10 ||

	    adev->asic_type == CHIP_SIENNA_CICHLID)

		psp_sysfs_fini(adev);



	return 0;
@@ -1750,6 +1751,12 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 
	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:

		*type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;

		break;

	case AMDGPU_UCODE_ID_RLC_IRAM:

		*type = GFX_FW_TYPE_RLC_IRAM;

		break;

	case AMDGPU_UCODE_ID_RLC_DRAM:

		*type = GFX_FW_TYPE_RLC_DRAM_BOOT;

		break;

	case AMDGPU_UCODE_ID_SMC:

		*type = GFX_FW_TYPE_SMU;

		break;

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+2 −2
Original line number Diff line number Diff line
@@ -1986,7 +1986,8 @@ static int amdgpu_ras_check_asic_type(struct amdgpu_device *adev) 
{

	if (adev->asic_type != CHIP_VEGA10 &&

		adev->asic_type != CHIP_VEGA20 &&

		adev->asic_type != CHIP_ARCTURUS)

		adev->asic_type != CHIP_ARCTURUS &&

		adev->asic_type != CHIP_SIENNA_CICHLID)

		return 1;

	else

		return 0;
@@ -2030,7 +2031,6 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev, 


	*supported = amdgpu_ras_enable == 0 ?

			0 : *hw_supported & amdgpu_ras_mask;



	adev->ras_features = *supported;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h

+4 −0
Original line number Diff line number Diff line
@@ -168,12 +168,16 @@ struct amdgpu_rlc { 
	u32 save_restore_list_cntl_size_bytes;

	u32 save_restore_list_gpm_size_bytes;

	u32 save_restore_list_srm_size_bytes;

	u32 rlc_iram_ucode_size_bytes;

	u32 rlc_dram_ucode_size_bytes;



	u32 *register_list_format;

	u32 *register_restore;

	u8 *save_restore_list_cntl;

	u8 *save_restore_list_gpm;

	u8 *save_restore_list_srm;

	u8 *rlc_iram_ucode;

	u8 *rlc_dram_ucode;



	bool is_rlc_v2_1;

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c

+10 −0
Original line number Diff line number Diff line
@@ -500,6 +500,8 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 
	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_IRAM &&

	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_DRAM &&

		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&

		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV &&

		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) {
@@ -556,6 +558,14 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 
		ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;

		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_IRAM) {

		ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;

		memcpy(ucode->kaddr, adev->gfx.rlc.rlc_iram_ucode,

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_DRAM) {

		ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;

		memcpy(ucode->kaddr, adev->gfx.rlc.rlc_dram_ucode,

		       ucode->ucode_size);

	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) {

		ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);

		memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +

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