Merge tag 'clk-meson-fixes-v5.4-1' of https://github.com/BayLibre/clk-meson into clk-fixes (3d883e89) · Commits · 戴 / test

drivers/clk/meson/g12a.c

+11 −2

Original line number	Diff line number	Diff line
		@@ -343,6 +343,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = {
		.offset = HHI_SYS_CPU_CLK_CNTL0,
		.mask = 0x3,
		.shift = 0,
		.flags = CLK_MUX_ROUND_CLOSEST,
		},
		.hw.init = &(struct clk_init_data){
		.name = "cpu_clk_dyn0_sel",
		@@ -353,8 +354,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = {
		{ .hw = &g12a_fclk_div3.hw },
		},
		.num_parents = 3,
		/* This sub-tree is used a parking clock */
		.flags = CLK_SET_RATE_NO_REPARENT,
		.flags = CLK_SET_RATE_PARENT,
		},
		};

		@@ -410,6 +410,7 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = {
		.offset = HHI_SYS_CPU_CLK_CNTL0,
		.mask = 0x1,
		.shift = 2,
		.flags = CLK_MUX_ROUND_CLOSEST,
		},
		.hw.init = &(struct clk_init_data){
		.name = "cpu_clk_dyn0",
		@@ -466,6 +467,7 @@ static struct clk_regmap g12a_cpu_clk_dyn = {
		.offset = HHI_SYS_CPU_CLK_CNTL0,
		.mask = 0x1,
		.shift = 10,
		.flags = CLK_MUX_ROUND_CLOSEST,
		},
		.hw.init = &(struct clk_init_data){
		.name = "cpu_clk_dyn",
		@@ -485,6 +487,7 @@ static struct clk_regmap g12a_cpu_clk = {
		.offset = HHI_SYS_CPU_CLK_CNTL0,
		.mask = 0x1,
		.shift = 11,
		.flags = CLK_MUX_ROUND_CLOSEST,
		},
		.hw.init = &(struct clk_init_data){
		.name = "cpu_clk",
		@@ -504,6 +507,7 @@ static struct clk_regmap g12b_cpu_clk = {
		.offset = HHI_SYS_CPU_CLK_CNTL0,
		.mask = 0x1,
		.shift = 11,
		.flags = CLK_MUX_ROUND_CLOSEST,
		},
		.hw.init = &(struct clk_init_data){
		.name = "cpu_clk",
		@@ -523,6 +527,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = {
		.offset = HHI_SYS_CPUB_CLK_CNTL,
		.mask = 0x3,
		.shift = 0,
		.flags = CLK_MUX_ROUND_CLOSEST,
		},
		.hw.init = &(struct clk_init_data){
		.name = "cpub_clk_dyn0_sel",
		@@ -533,6 +538,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = {
		{ .hw = &g12a_fclk_div3.hw },
		},
		.num_parents = 3,
		.flags = CLK_SET_RATE_PARENT,
		},
		};

		@@ -567,6 +573,7 @@ static struct clk_regmap g12b_cpub_clk_postmux0 = {
		.offset = HHI_SYS_CPUB_CLK_CNTL,
		.mask = 0x1,
		.shift = 2,
		.flags = CLK_MUX_ROUND_CLOSEST,
		},
		.hw.init = &(struct clk_init_data){
		.name = "cpub_clk_dyn0",
		@@ -644,6 +651,7 @@ static struct clk_regmap g12b_cpub_clk_dyn = {
		.offset = HHI_SYS_CPUB_CLK_CNTL,
		.mask = 0x1,
		.shift = 10,
		.flags = CLK_MUX_ROUND_CLOSEST,
		},
		.hw.init = &(struct clk_init_data){
		.name = "cpub_clk_dyn",
		@@ -663,6 +671,7 @@ static struct clk_regmap g12b_cpub_clk = {
		.offset = HHI_SYS_CPUB_CLK_CNTL,
		.mask = 0x1,
		.shift = 11,
		.flags = CLK_MUX_ROUND_CLOSEST,
		},
		.hw.init = &(struct clk_init_data){
		.name = "cpub_clk",

drivers/clk/meson/gxbb.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -935,6 +935,7 @@ static struct clk_regmap gxbb_sar_adc_clk_div = {
		&gxbb_sar_adc_clk_sel.hw
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		},
		};

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