Commit 3c8b2e2c authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'mvebu-dt-5.5-1' of git://git.infradead.org/linux-mvebu into arm/dt

mvebu dt for 5.5 (part 1)

 - Enable L2 cache parity and ECC on a Armada XP SoC family and allow
   to use in on the Armada 38x SoCs too.
 - Use correct name for the rs5c372a on synology (Kirkwood based)
 - Rename "sa-sram" node to "sram" on dove

* tag 'mvebu-dt-5.5-1' of git://git.infradead.org/linux-mvebu:
  ARM: dts: armada-xp: add label to sdram-controller node
  ARM: dts: mvebu: add sdram controller node to Armada-38x
  ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg
  ARM: dts: dove: Rename "sa-sram" node to "sram"
  ARM: dts: kirkwood: synology: Fix rs5c372 RTC entry

Link: https://lore.kernel.org/r/8736f44q9l.fsf@FE-laptop


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents fc711fdf 90b9dc96
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+5 −0
Original line number Diff line number Diff line
@@ -103,6 +103,11 @@
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			sdramc: sdramc@1400 {
				compatible = "marvell,armada-xp-sdram-controller";
				reg = <0x1400 0x500>;
			};

			L2: cache-controller@8000 {
				compatible = "arm,pl310-cache";
				reg = <0x8000 0x1000>;
+1 −1
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@@ -90,7 +90,7 @@
		};

		internal-regs {
			sdramc@1400 {
			sdramc: sdramc@1400 {
				compatible = "marvell,armada-xp-sdram-controller";
				reg = <0x1400 0x500>;
			};
+5 −0
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@@ -33,6 +33,11 @@
	};
};

&L2 {
	arm,parity-enable;
	marvell,ecc-enable;
};

&devbus_bootcs {
	status = "okay";

+1 −1
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@@ -36,7 +36,7 @@
		};

		internal-regs {
			sdramc@1400 {
			sdramc: sdramc@1400 {
				compatible = "marvell,armada-xp-sdram-controller";
				reg = <0x1400 0x500>;
			};
+1 −1
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@@ -784,7 +784,7 @@
				status = "disabled";
			};

			crypto_sram: sa-sram@ffffe000 {
			crypto_sram: sram@ffffe000 {
				compatible = "mmio-sram";
				reg = <0xffffe000 0x800>;
				clocks = <&gate_clk 15>;
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