Commit fc711fdf authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'tegra-for-5.5-arm64-dt' of... 

Merge tag 'tegra-for-5.5-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.5-rc1

Adds support for DP and XUSB on various boards, enables SMMU support for
more devices and fixes a couple of DTC warnings and inconsistencies that
are reported at runtime.

These changes along with some of the driver changes in other branches
allow suspend/resume support on Tegra210 devices (e.g. Jetson TX1 and
Jetson Nano).

* tag 'tegra-for-5.5-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits)
  arm64: tegra: Add Jetson Nano SC7 timings
  arm64: tegra: Add Jetson TX1 SC7 timings
  arm64: tegra: Enable wake from deep sleep on RTC alarm
  arm64: tegra: Add PMU on Tegra210
  arm64: tegra: Add blank lines for better readability
  arm64: tegra: Enable DisplayPort on Jetson AGX Xavier
  arm64: tegra: p2888: Rename regulators for consistency
  arm64: tegra: Enable DP support on Jetson TX2
  arm64: tegra: Fix compatible for SOR1
  arm64: tegra: Enable DP support on Jetson Nano
  arm64: tegra: Add SOR0_OUT clock on Tegra210
  arm64: tegra: Assume no CLKREQ presence by default
  arm64: tegra: Enable SMMU for VIC on Tegra186
  arm64: tegra: Enable XUSB host controller on Jetson TX2
  arm64: tegra: Enable SMMU for XUSB host on Tegra186
  arm64: tegra: Enable XUSB pad controller on Jetson TX2
  arm64: tegra: Add ethernet alias on Jetson AGX Xavier
  arm64: tegra: Fix compatible string for EQOS on Tegra194
  arm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERM
  arm64: tegra: Fix base address for SOR1 on Tegra194
  ...

Link: https://lore.kernel.org/r/20191102144521.3863321-8-thierry.reding@gmail.com


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 2687aa23 47b4e129

arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts

+8 −4
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ 
	};



	padctl@3520000 {

		status = "disabled";

		status = "okay";



		avdd-pll-erefeut-supply = <&vdd_1v8_pll>;

		avdd-usb-supply = <&vdd_3v3_sys>;
@@ -193,7 +193,7 @@ 
	};



	usb@3530000 {

		status = "disabled";

		status = "okay";



		phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,

		       <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
@@ -253,10 +253,14 @@ 
			status = "disabled";

		};



		/* DP on E3320 */

		sor@15540000 {

			status = "disabled";

			status = "okay";



			avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;

			vdd-hdmi-dp-pll = <&vdd_1v8_ap>;



			nvidia,dpaux = <&dpaux1>;

			nvidia,dpaux = <&dpaux>;

		};



		sor@15580000 {

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+3 −1
Original line number Diff line number Diff line
@@ -525,6 +525,7 @@ 
		      <0x0 0x03538000 0x0 0x1000>;

		reg-names = "hcd", "fpci";



		iommus = <&smmu TEGRA186_SID_XUSB_HOST>;

		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
@@ -1018,6 +1019,7 @@ 
			reset-names = "vic";



			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;

			iommus = <&smmu TEGRA186_SID_VIC>;

		};



		dsib: dsi@15400000 {
@@ -1060,7 +1062,7 @@ 
		};



		sor1: sor@15580000 {

			compatible = "nvidia,tegra186-sor1";

			compatible = "nvidia,tegra186-sor";

			reg = <0x15580000 0x10000>;

			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&bpmp TEGRA186_CLK_SOR1>,

arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi

+18 −18
Original line number Diff line number Diff line
@@ -8,17 +8,18 @@ 
	compatible = "nvidia,p2888", "nvidia,tegra194";



	aliases {

		sdhci0 = "/cbb/sdhci@3460000";

		sdhci1 = "/cbb/sdhci@3400000";

		ethernet0 = "/cbb@0/ethernet@2490000";

		sdhci0 = "/cbb@0/sdhci@3460000";

		sdhci1 = "/cbb@0/sdhci@3400000";

		serial0 = &tcu;

		i2c0 = "/bpmp/i2c";

		i2c1 = "/cbb/i2c@3160000";

		i2c2 = "/cbb/i2c@c240000";

		i2c3 = "/cbb/i2c@3180000";

		i2c4 = "/cbb/i2c@3190000";

		i2c5 = "/cbb/i2c@31c0000";

		i2c6 = "/cbb/i2c@c250000";

		i2c7 = "/cbb/i2c@31e0000";

		i2c1 = "/cbb@0/i2c@3160000";

		i2c2 = "/cbb@0/i2c@c240000";

		i2c3 = "/cbb@0/i2c@3180000";

		i2c4 = "/cbb@0/i2c@3190000";

		i2c5 = "/cbb@0/i2c@31c0000";

		i2c6 = "/cbb@0/i2c@c250000";

		i2c7 = "/cbb@0/i2c@31e0000";

	};



	chosen {
@@ -26,7 +27,7 @@ 
		stdout-path = "serial0:115200n8";

	};



	cbb {

	cbb@0 {

		ethernet@2490000 {

			status = "okay";
@@ -168,7 +169,7 @@ 
					in-ldo7-8-supply = <&vdd_1v8ls>;



					vdd_1v0: sd0 {

						regulator-name = "VDD_1V0";

						regulator-name = "VDDIO_SYS_1V0";

						regulator-min-microvolt = <1000000>;

						regulator-max-microvolt = <1000000>;

						regulator-always-on;
@@ -176,7 +177,7 @@ 
					};



					vdd_1v8hs: sd1 {

						regulator-name = "VDD_1V8HS";

						regulator-name = "VDDIO_SYS_1V8HS";

						regulator-min-microvolt = <1800000>;

						regulator-max-microvolt = <1800000>;

						regulator-always-on;
@@ -184,7 +185,7 @@ 
					};



					vdd_1v8ls: sd2 {

						regulator-name = "VDD_1V8LS";

						regulator-name = "VDDIO_SYS_1V8LS";

						regulator-min-microvolt = <1800000>;

						regulator-max-microvolt = <1800000>;

						regulator-always-on;
@@ -192,7 +193,7 @@ 
					};



					vdd_1v8ao: sd3 {

						regulator-name = "VDD_1V8AO";

						regulator-name = "VDDIO_AO_1V8";

						regulator-min-microvolt = <1800000>;

						regulator-max-microvolt = <1800000>;

						regulator-always-on;
@@ -216,7 +217,7 @@ 
					};



					ldo2 {

						regulator-name = "VDD_AO_3V3";

						regulator-name = "VDDIO_AO_3V3";

						regulator-min-microvolt = <3300000>;

						regulator-max-microvolt = <3300000>;

						regulator-always-on;
@@ -242,7 +243,7 @@ 
					};



					ldo7 {

						regulator-name = "VDD_CSI_1V2";

						regulator-name = "AVDD_CSI_1V2";

						regulator-min-microvolt = <1200000>;

						regulator-max-microvolt = <1200000>;

					};
@@ -309,9 +310,8 @@ 
			regulator-name = "VDD_12V";

			regulator-min-microvolt = <1200000>;

			regulator-max-microvolt = <1200000>;

			gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;

			gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>;

			regulator-boot-on;

			enable-active-low;

		};

	};

};

arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts

+31 −2
Original line number Diff line number Diff line
@@ -10,8 +10,8 @@ 
	model = "NVIDIA Jetson AGX Xavier Developer Kit";

	compatible = "nvidia,p2972-0000", "nvidia,tegra194";



	cbb {

		aconnect {

	cbb@0 {

		aconnect@2900000 {

			status = "okay";



			dma-controller@2930000 {
@@ -46,10 +46,39 @@ 
				status = "okay";

			};



			dpaux@155c0000 {

				status = "okay";

			};



			dpaux@155d0000 {

				status = "okay";

			};



			dpaux@155e0000 {

				status = "okay";

			};



			/* DP0 */

			sor@15b00000 {

				status = "okay";



				avdd-io-hdmi-dp-supply = <&vdd_1v0>;

				vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>;



				nvidia,dpaux = <&dpaux0>;

			};



			/* DP1 */

			sor@15b40000 {

				status = "okay";



				avdd-io-hdmi-dp-supply = <&vdd_1v0>;

				vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>;



				nvidia,dpaux = <&dpaux1>;

			};



			/* HDMI */

			sor@15b80000 {

				status = "okay";

arch/arm64/boot/dts/nvidia/tegra194.dtsi

+149 −22
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
	#size-cells = <2>;



	/* control backbone */

	cbb {

	cbb@0 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;
@@ -39,7 +39,8 @@ 
		};



		ethernet@2490000 {

			compatible = "nvidia,tegra186-eqos",

			compatible = "nvidia,tegra194-eqos",

				     "nvidia,tegra186-eqos",

				     "snps,dwc-qos-ethernet-4.10";

			reg = <0x02490000 0x10000>;

			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
@@ -60,7 +61,7 @@ 
			snps,rxpbl = <8>;

		};



		aconnect {

		aconnect@2900000 {

			compatible = "nvidia,tegra194-aconnect",

				     "nvidia,tegra210-aconnect";

			clocks = <&bpmp TEGRA194_CLK_APE>,
@@ -1078,7 +1079,7 @@ 


			sor1: sor@15b40000 {

				compatible = "nvidia,tegra194-sor";

				reg = <0x155c0000 0x40000>;

				reg = <0x15b40000 0x40000>;

				interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,

					 <&bpmp TEGRA194_CLK_SOR1_OUT>,
@@ -1185,7 +1186,6 @@ 


		nvidia,bpmp = <&bpmp 1>;



		supports-clkreq;

		nvidia,aspm-cmrt-us = <60>;

		nvidia,aspm-pwr-on-t-us = <20>;

		nvidia,aspm-l0s-entrance-latency-us = <3>;
@@ -1231,7 +1231,6 @@ 


		nvidia,bpmp = <&bpmp 2>;



		supports-clkreq;

		nvidia,aspm-cmrt-us = <60>;

		nvidia,aspm-pwr-on-t-us = <20>;

		nvidia,aspm-l0s-entrance-latency-us = <3>;
@@ -1277,7 +1276,6 @@ 


		nvidia,bpmp = <&bpmp 3>;



		supports-clkreq;

		nvidia,aspm-cmrt-us = <60>;

		nvidia,aspm-pwr-on-t-us = <20>;

		nvidia,aspm-l0s-entrance-latency-us = <3>;
@@ -1323,7 +1321,6 @@ 


		nvidia,bpmp = <&bpmp 4>;



		supports-clkreq;

		nvidia,aspm-cmrt-us = <60>;

		nvidia,aspm-pwr-on-t-us = <20>;

		nvidia,aspm-l0s-entrance-latency-us = <3>;
@@ -1369,7 +1366,6 @@ 


		nvidia,bpmp = <&bpmp 0>;



		supports-clkreq;

		nvidia,aspm-cmrt-us = <60>;

		nvidia,aspm-pwr-on-t-us = <20>;

		nvidia,aspm-l0s-entrance-latency-us = <3>;
@@ -1419,7 +1415,6 @@ 
		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;



		supports-clkreq;

		nvidia,aspm-cmrt-us = <60>;

		nvidia,aspm-pwr-on-t-us = <20>;

		nvidia,aspm-l0s-entrance-latency-us = <3>;
@@ -1478,60 +1473,192 @@ 
		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

		cpu0_0: cpu@0 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x10000>;

			reg = <0x000>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_0>;

		};



		cpu@1 {

		cpu0_1: cpu@1 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x10001>;

			reg = <0x001>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_0>;

		};



		cpu@2 {

		cpu1_0: cpu@100 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x100>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_1>;

		};



		cpu@3 {

		cpu1_1: cpu@101 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x101>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_1>;

		};



		cpu@4 {

		cpu2_0: cpu@200 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x200>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_2>;

		};



		cpu@5 {

		cpu2_1: cpu@201 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x201>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_2>;

		};



		cpu@6 {

		cpu3_0: cpu@300 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x10300>;

			reg = <0x300>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_3>;

		};



		cpu@7 {

		cpu3_1: cpu@301 {

			compatible = "nvidia,tegra194-carmel";

			device_type = "cpu";

			reg = <0x10301>;

			reg = <0x301>;

			enable-method = "psci";

			i-cache-size = <131072>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <65536>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&l2c_3>;

		};



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&cpu0_0>;

				};



				core1 {

					cpu = <&cpu0_1>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&cpu1_0>;

				};



				core1 {

					cpu = <&cpu1_1>;

				};

			};



			cluster2 {

				core0 {

					cpu = <&cpu2_0>;

				};



				core1 {

					cpu = <&cpu2_1>;

				};

			};



			cluster3 {

				core0 {

					cpu = <&cpu3_0>;

				};



				core1 {

					cpu = <&cpu3_1>;

				};

			};

		};



		l2c_0: l2-cache0 {

			cache-size = <2097152>;

			cache-line-size = <64>;

			cache-sets = <2048>;

			next-level-cache = <&l3c>;

		};



		l2c_1: l2-cache1 {

			cache-size = <2097152>;

			cache-line-size = <64>;

			cache-sets = <2048>;

			next-level-cache = <&l3c>;

		};



		l2c_2: l2-cache2 {

			cache-size = <2097152>;

			cache-line-size = <64>;

			cache-sets = <2048>;

			next-level-cache = <&l3c>;

		};



		l2c_3: l2-cache3 {

			cache-size = <2097152>;

			cache-line-size = <64>;

			cache-sets = <2048>;

			next-level-cache = <&l3c>;

		};



		l3c: l3-cache {

			cache-size = <4194304>;

			cache-line-size = <64>;

			cache-sets = <4096>;

		};

	};

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