Commit 3b91a935 authored by Aditya Swarup's avatar Aditya Swarup Committed by Jani Nikula
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drm/i915/cnl: Fix CNL macros for Voltage Swing programming 



CNL macros for register groups CNL_PORT_TX_DW2_* / CNL_PORT_TX_DW5_* are
configured incorrectly wrt definition of _CNL_PORT_TX_DW_GRP.

v2: Jani suggested to keep the macros organized semantically i.e., by
function, secondarily by port/pipe/transcoder.->(dw, port)

Fixes: 4e53840f ("drm/i915/icl: Introduce new macros to get combophy registers")
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: default avatarAditya Swarup <aditya.swarup@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190110230844.9213-1-aditya.swarup@intel.com


(cherry picked from commit b14c06ec)
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 9659c1af

drivers/gpu/drm/i915/i915_reg.h

+7 −7
Original line number Diff line number Diff line
@@ -1790,7 +1790,7 @@ enum i915_power_well_id { 
#define _CNL_PORT_TX_C_LN0_OFFSET		0x162C40

#define _CNL_PORT_TX_D_LN0_OFFSET		0x162E40

#define _CNL_PORT_TX_F_LN0_OFFSET		0x162840

#define _CNL_PORT_TX_DW_GRP(port, dw)	(_PICK((port), \

#define _CNL_PORT_TX_DW_GRP(dw, port)	(_PICK((port), \

					       _CNL_PORT_TX_AE_GRP_OFFSET, \

					       _CNL_PORT_TX_B_GRP_OFFSET, \

					       _CNL_PORT_TX_B_GRP_OFFSET, \
@@ -1798,7 +1798,7 @@ enum i915_power_well_id { 
					       _CNL_PORT_TX_AE_GRP_OFFSET, \

					       _CNL_PORT_TX_F_GRP_OFFSET) + \

					       4 * (dw))

#define _CNL_PORT_TX_DW_LN0(port, dw)	(_PICK((port), \

#define _CNL_PORT_TX_DW_LN0(dw, port)	(_PICK((port), \

					       _CNL_PORT_TX_AE_LN0_OFFSET, \

					       _CNL_PORT_TX_B_LN0_OFFSET, \

					       _CNL_PORT_TX_B_LN0_OFFSET, \
@@ -1834,9 +1834,9 @@ enum i915_power_well_id { 


#define _CNL_PORT_TX_DW4_LN0_AE		0x162450

#define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0

#define CNL_PORT_TX_DW4_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 4))

#define CNL_PORT_TX_DW4_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 4))

#define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \

#define CNL_PORT_TX_DW4_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))

#define CNL_PORT_TX_DW4_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))

#define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \

					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \

						    _CNL_PORT_TX_DW4_LN0_AE)))

#define ICL_PORT_TX_DW4_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(4, port))
@@ -1864,8 +1864,8 @@ enum i915_power_well_id { 
#define   RTERM_SELECT(x)		((x) << 3)

#define   RTERM_SELECT_MASK		(0x7 << 3)



#define CNL_PORT_TX_DW7_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 7))

#define CNL_PORT_TX_DW7_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 7))

#define CNL_PORT_TX_DW7_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))

#define CNL_PORT_TX_DW7_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))

#define ICL_PORT_TX_DW7_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(7, port))

#define ICL_PORT_TX_DW7_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(7, port))

#define ICL_PORT_TX_DW7_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))

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