Commit 4e53840f authored by Lucas De Marchi's avatar Lucas De Marchi Committed by Rodrigo Vivi
Browse files

drm/i915/icl: Introduce new macros to get combophy registers 



combo-phy register instances are at same offset from base for each
combo-phy port, i.e.

Port A base offset: 0x16200
Port B base offset: 0x6C000

All the other addresses for both ports can be derived by calculating
offset to these base addresses.

PORT_CL_DW_OFFSET	0x0
PORT_CL_DW<x>		0 + x * 4

PORT_COMP_OFFSET	0x100
PORT_COMP_DW<x>		0x100 + x * 4

PORT_PCS_AUX_OFFSET     0x300
PORT_PCS_GRP_OFFSET     0x600
PORT_PCS_LN<y>_OFFSET   0x800 + y * 0x100

PORT_TX_AUX_OFFSET      0x380
PORT_TX_GRP_OFFSET      0x680
PORT_TX_LN<y>_OFFSET    0x880 + y * 0x100

And inside each PORT_TX_[AUX|GRP|LN] we add `dw * 4`.

Based on original patch by Mahesh Kumar <mahesh1.kumar@intel.com>.

v2: make port, dw and ln arguments follow the order in
    register's name

Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181016023517.8576-1-lucas.demarchi@intel.com
parent d72e84cc

drivers/gpu/drm/i915/i915_reg.h

+59 −104
Original line number Original line Diff line number Diff line
@@ -1658,20 +1658,21 @@ enum i915_power_well_id { 
/*

/*

 * CNL/ICL Port/COMBO-PHY Registers

 * CNL/ICL Port/COMBO-PHY Registers

 */

 */

#define _ICL_COMBOPHY_A			0x162000

#define _ICL_COMBOPHY_B			0x6C000

#define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \

					      _ICL_COMBOPHY_B)



/* CNL/ICL Port CL_DW registers */

/* CNL/ICL Port CL_DW registers */

#define _ICL_PORT_CL_DW(dw, port)	(_ICL_COMBOPHY(port) + \

					 4 * (dw))



#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)

#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)

#define _ICL_PORT_CL_DW5_A	0x162014

#define ICL_PORT_CL_DW5(port)		_MMIO(_ICL_PORT_CL_DW(5, port))

#define _ICL_PORT_CL_DW5_B	0x6C014

#define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \

						 _ICL_PORT_CL_DW5_B)

#define   CL_POWER_DOWN_ENABLE		(1 << 4)

#define   CL_POWER_DOWN_ENABLE		(1 << 4)

#define   SUS_CLOCK_CONFIG		(3 << 0)

#define   SUS_CLOCK_CONFIG		(3 << 0)





#define _CNL_PORT_CL_DW10_A		0x162028

#define ICL_PORT_CL_DW10(port)		_MMIO(_ICL_PORT_CL_DW(10, port))

#define _ICL_PORT_CL_DW10_B		0x6c028

#define ICL_PORT_CL_DW10(port)		_MMIO_PORT(port,	\

						   _CNL_PORT_CL_DW10_A, \

						   _ICL_PORT_CL_DW10_B)

#define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)

#define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)

#define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25

#define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25

#define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)

#define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
@@ -1687,31 +1688,23 @@ enum i915_power_well_id { 
#define  PWR_DOWN_LN_MASK		(0xf << 4)

#define  PWR_DOWN_LN_MASK		(0xf << 4)

#define  PWR_DOWN_LN_SHIFT		4

#define  PWR_DOWN_LN_SHIFT		4





#define _ICL_PORT_CL_DW12_A		0x162030

#define ICL_PORT_CL_DW12(port)		_MMIO(_ICL_PORT_CL_DW(12, port))

#define _ICL_PORT_CL_DW12_B		0x6C030

#define   ICL_LANE_ENABLE_AUX		(1 << 0)

#define   ICL_LANE_ENABLE_AUX		(1 << 0)

#define ICL_PORT_CL_DW12(port)		_MMIO_PORT((port),		\

						   _ICL_PORT_CL_DW12_A, \

						   _ICL_PORT_CL_DW12_B)





/* CNL/ICL Port COMP_DW registers */

/* CNL/ICL Port COMP_DW registers */

#define _ICL_PORT_COMP			0x100

#define _ICL_PORT_COMP_DW(dw, port)	(_ICL_COMBOPHY(port) + \

					 _ICL_PORT_COMP + 4 * (dw))



#define CNL_PORT_COMP_DW0		_MMIO(0x162100)

#define CNL_PORT_COMP_DW0		_MMIO(0x162100)

#define _ICL_PORT_COMP_DW0_A		0x162100

#define ICL_PORT_COMP_DW0(port)		_MMIO(_ICL_PORT_COMP_DW(0, port))

#define _ICL_PORT_COMP_DW0_B		0x6C100

#define ICL_PORT_COMP_DW0(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \

							 _ICL_PORT_COMP_DW0_B)

#define   COMP_INIT			(1 << 31)

#define   COMP_INIT			(1 << 31)





#define CNL_PORT_COMP_DW1		_MMIO(0x162104)

#define CNL_PORT_COMP_DW1		_MMIO(0x162104)

#define _ICL_PORT_COMP_DW1_A		0x162104

#define ICL_PORT_COMP_DW1(port)		_MMIO(_ICL_PORT_COMP_DW(1, port))

#define _ICL_PORT_COMP_DW1_B		0x6C104



#define ICL_PORT_COMP_DW1(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \

							 _ICL_PORT_COMP_DW1_B)

#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)

#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)

#define _ICL_PORT_COMP_DW3_A		0x16210C

#define ICL_PORT_COMP_DW3(port)		_MMIO(_ICL_PORT_COMP_DW(3, port))

#define _ICL_PORT_COMP_DW3_B		0x6C10C

#define ICL_PORT_COMP_DW3(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \

							 _ICL_PORT_COMP_DW3_B)

#define   PROCESS_INFO_DOT_0		(0 << 26)

#define   PROCESS_INFO_DOT_0		(0 << 26)

#define   PROCESS_INFO_DOT_1		(1 << 26)

#define   PROCESS_INFO_DOT_1		(1 << 26)

#define   PROCESS_INFO_DOT_4		(2 << 26)

#define   PROCESS_INFO_DOT_4		(2 << 26)
@@ -1724,17 +1717,10 @@ enum i915_power_well_id { 
#define   VOLTAGE_INFO_SHIFT		24

#define   VOLTAGE_INFO_SHIFT		24





#define CNL_PORT_COMP_DW9		_MMIO(0x162124)

#define CNL_PORT_COMP_DW9		_MMIO(0x162124)

#define _ICL_PORT_COMP_DW9_A		0x162124

#define ICL_PORT_COMP_DW9(port)		_MMIO(_ICL_PORT_COMP_DW(9, port))

#define _ICL_PORT_COMP_DW9_B		0x6C124

#define ICL_PORT_COMP_DW9(port)		_MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \

							 _ICL_PORT_COMP_DW9_B)





#define CNL_PORT_COMP_DW10		_MMIO(0x162128)

#define CNL_PORT_COMP_DW10		_MMIO(0x162128)

#define _ICL_PORT_COMP_DW10_A		0x162128

#define ICL_PORT_COMP_DW10(port)	_MMIO(_ICL_PORT_COMP_DW(10, port))

#define _ICL_PORT_COMP_DW10_B		0x6C128

#define ICL_PORT_COMP_DW10(port)	_MMIO_PORT(port, \

						   _ICL_PORT_COMP_DW10_A, \

						   _ICL_PORT_COMP_DW10_B)





/* CNL/ICL Port PCS registers */

/* CNL/ICL Port PCS registers */

#define _CNL_PORT_PCS_DW1_GRP_AE	0x162304

#define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
@@ -1754,7 +1740,6 @@ enum i915_power_well_id { 
						    _CNL_PORT_PCS_DW1_GRP_D, \

						    _CNL_PORT_PCS_DW1_GRP_D, \

						    _CNL_PORT_PCS_DW1_GRP_AE, \

						    _CNL_PORT_PCS_DW1_GRP_AE, \

						    _CNL_PORT_PCS_DW1_GRP_F))

						    _CNL_PORT_PCS_DW1_GRP_F))



#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \

#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \

						    _CNL_PORT_PCS_DW1_LN0_AE, \

						    _CNL_PORT_PCS_DW1_LN0_AE, \

						    _CNL_PORT_PCS_DW1_LN0_B, \

						    _CNL_PORT_PCS_DW1_LN0_B, \
@@ -1763,21 +1748,18 @@ enum i915_power_well_id { 
						    _CNL_PORT_PCS_DW1_LN0_AE, \

						    _CNL_PORT_PCS_DW1_LN0_AE, \

						    _CNL_PORT_PCS_DW1_LN0_F))

						    _CNL_PORT_PCS_DW1_LN0_F))





#define _ICL_PORT_PCS_DW1_GRP_A		0x162604

#define _ICL_PORT_PCS_AUX		0x300

#define _ICL_PORT_PCS_DW1_GRP_B		0x6C604

#define _ICL_PORT_PCS_GRP		0x600

#define _ICL_PORT_PCS_DW1_LN0_A		0x162804

#define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)

#define _ICL_PORT_PCS_DW1_LN0_B		0x6C804

#define _ICL_PORT_PCS_DW_AUX(dw, port)	(_ICL_COMBOPHY(port) + \

#define _ICL_PORT_PCS_DW1_AUX_A		0x162304

					 _ICL_PORT_PCS_AUX + 4 * (dw))

#define _ICL_PORT_PCS_DW1_AUX_B		0x6c304

#define _ICL_PORT_PCS_DW_GRP(dw, port)	(_ICL_COMBOPHY(port) + \

#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT(port,\

					 _ICL_PORT_PCS_GRP + 4 * (dw))

						   _ICL_PORT_PCS_DW1_GRP_A, \

#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \

						   _ICL_PORT_PCS_DW1_GRP_B)

					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))

#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT(port, \

#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, port))

						   _ICL_PORT_PCS_DW1_LN0_A, \

#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, port))

						   _ICL_PORT_PCS_DW1_LN0_B)

#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))

#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO_PORT(port, \

						   _ICL_PORT_PCS_DW1_AUX_A, \

						   _ICL_PORT_PCS_DW1_AUX_B)

#define   COMMON_KEEPER_EN		(1 << 26)

#define   COMMON_KEEPER_EN		(1 << 26)





/* CNL/ICL Port TX registers */

/* CNL/ICL Port TX registers */
@@ -1808,23 +1790,22 @@ enum i915_power_well_id { 
					       _CNL_PORT_TX_F_LN0_OFFSET) + \

					       _CNL_PORT_TX_F_LN0_OFFSET) + \

					       4 * (dw))

					       4 * (dw))





#define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 2))

#define _ICL_PORT_TX_AUX		0x380

#define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 2))

#define _ICL_PORT_TX_GRP		0x680

#define _ICL_PORT_TX_DW2_GRP_A		0x162688

#define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)

#define _ICL_PORT_TX_DW2_GRP_B		0x6C688



#define _ICL_PORT_TX_DW2_LN0_A		0x162888

#define _ICL_PORT_TX_DW_AUX(dw, port)	(_ICL_COMBOPHY(port) + \

#define _ICL_PORT_TX_DW2_LN0_B		0x6C888

					 _ICL_PORT_TX_AUX + 4 * (dw))

#define _ICL_PORT_TX_DW2_AUX_A		0x162388

#define _ICL_PORT_TX_DW_GRP(dw, port)	(_ICL_COMBOPHY(port) + \

#define _ICL_PORT_TX_DW2_AUX_B		0x6c388

					 _ICL_PORT_TX_GRP + 4 * (dw))

#define ICL_PORT_TX_DW2_GRP(port)	_MMIO_PORT(port, \

#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \

						   _ICL_PORT_TX_DW2_GRP_A, \

					  _ICL_PORT_TX_LN(ln) + 4 * (dw))

						   _ICL_PORT_TX_DW2_GRP_B)



#define ICL_PORT_TX_DW2_LN0(port)	_MMIO_PORT(port, \

#define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(2, port))

						   _ICL_PORT_TX_DW2_LN0_A, \

#define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(2, port))

						   _ICL_PORT_TX_DW2_LN0_B)

#define ICL_PORT_TX_DW2_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(2, port))

#define ICL_PORT_TX_DW2_AUX(port)	_MMIO_PORT(port, \

#define ICL_PORT_TX_DW2_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(2, port))

						   _ICL_PORT_TX_DW2_AUX_A, \

#define ICL_PORT_TX_DW2_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))

						   _ICL_PORT_TX_DW2_AUX_B)

#define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)

#define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)

#define   SWING_SEL_UPPER_MASK		(1 << 15)

#define   SWING_SEL_UPPER_MASK		(1 << 15)

#define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)

#define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
@@ -1841,24 +1822,10 @@ enum i915_power_well_id { 
#define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \

#define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \

					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \

					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \

						    _CNL_PORT_TX_DW4_LN0_AE)))

						    _CNL_PORT_TX_DW4_LN0_AE)))

#define _ICL_PORT_TX_DW4_GRP_A		0x162690

#define ICL_PORT_TX_DW4_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(4, port))

#define _ICL_PORT_TX_DW4_GRP_B		0x6C690

#define ICL_PORT_TX_DW4_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(4, port))

#define _ICL_PORT_TX_DW4_LN0_A		0x162890

#define ICL_PORT_TX_DW4_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, port))

#define _ICL_PORT_TX_DW4_LN1_A		0x162990

#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_ICL_PORT_TX_DW_LN(4, ln, port))

#define _ICL_PORT_TX_DW4_LN0_B		0x6C890

#define _ICL_PORT_TX_DW4_AUX_A		0x162390

#define _ICL_PORT_TX_DW4_AUX_B		0x6c390

#define ICL_PORT_TX_DW4_GRP(port)	_MMIO_PORT(port, \

						   _ICL_PORT_TX_DW4_GRP_A, \

						   _ICL_PORT_TX_DW4_GRP_B)

#define ICL_PORT_TX_DW4_LN(port, ln)	_MMIO(_PORT(port, \

						   _ICL_PORT_TX_DW4_LN0_A, \

						   _ICL_PORT_TX_DW4_LN0_B) + \

					     ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \

						      _ICL_PORT_TX_DW4_LN0_A)))

#define ICL_PORT_TX_DW4_AUX(port)	_MMIO_PORT(port, \

						   _ICL_PORT_TX_DW4_AUX_A, \

						   _ICL_PORT_TX_DW4_AUX_B)

#define   LOADGEN_SELECT		(1 << 31)

#define   LOADGEN_SELECT		(1 << 31)

#define   POST_CURSOR_1(x)		((x) << 12)

#define   POST_CURSOR_1(x)		((x) << 12)

#define   POST_CURSOR_1_MASK		(0x3F << 12)

#define   POST_CURSOR_1_MASK		(0x3F << 12)
@@ -1867,23 +1834,11 @@ enum i915_power_well_id { 
#define   CURSOR_COEFF(x)		((x) << 0)

#define   CURSOR_COEFF(x)		((x) << 0)

#define   CURSOR_COEFF_MASK		(0x3F << 0)

#define   CURSOR_COEFF_MASK		(0x3F << 0)





#define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP((port), 5))

#define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(5, port))

#define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0((port), 5))

#define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(5, port))

#define _ICL_PORT_TX_DW5_GRP_A		0x162694

#define ICL_PORT_TX_DW5_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(5, port))

#define _ICL_PORT_TX_DW5_GRP_B		0x6C694

#define ICL_PORT_TX_DW5_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(5, port))

#define _ICL_PORT_TX_DW5_LN0_A		0x162894

#define ICL_PORT_TX_DW5_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))

#define _ICL_PORT_TX_DW5_LN0_B		0x6C894

#define _ICL_PORT_TX_DW5_AUX_A		0x162394

#define _ICL_PORT_TX_DW5_AUX_B		0x6c394

#define ICL_PORT_TX_DW5_GRP(port)	_MMIO_PORT(port, \

						   _ICL_PORT_TX_DW5_GRP_A, \

						   _ICL_PORT_TX_DW5_GRP_B)

#define ICL_PORT_TX_DW5_LN0(port)	_MMIO_PORT(port, \

						   _ICL_PORT_TX_DW5_LN0_A, \

						   _ICL_PORT_TX_DW5_LN0_B)

#define ICL_PORT_TX_DW5_AUX(port)	_MMIO_PORT(port, \

						   _ICL_PORT_TX_DW5_AUX_A, \

						   _ICL_PORT_TX_DW5_AUX_B)

#define   TX_TRAINING_EN		(1 << 31)

#define   TX_TRAINING_EN		(1 << 31)

#define   TAP2_DISABLE			(1 << 30)

#define   TAP2_DISABLE			(1 << 30)

#define   TAP3_DISABLE			(1 << 29)

#define   TAP3_DISABLE			(1 << 29)

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