Commit 39f1622b authored by Carlo Caione's avatar Carlo Caione Committed by Shawn Guo
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arm64: dts: imx8mq: Add QuadSPI controller



Add a node for the Freescale/NXP QuadSPI controller and extend the AIPS3
memory range to accommodate the QuadSPI-memory region.

Signed-off-by: default avatarCarlo Caione <ccaione@baylibre.com>
Reviewed-by: default avatarLucas Stach <l.stach@pengutronix.de>
Reviewed-by: default avatarFabio Estevam <festevam@gmail.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 85761f45
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+16 −1
Original line number Diff line number Diff line
@@ -384,7 +384,8 @@
			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x30800000 0x30800000 0x400000>;
			ranges = <0x30800000 0x30800000 0x400000>,
				 <0x08000000 0x08000000 0x10000000>;

			ecspi1: spi@30820000 {
				#address-cells = <1>;
@@ -536,6 +537,20 @@
				status = "disabled";
			};

			qspi0: spi@30bb0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
				reg = <0x30bb0000 0x10000>,
				      <0x08000000 0x10000000>;
				reg-names = "QuadSPI", "QuadSPI-memory";
				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
					 <&clk IMX8MQ_CLK_QSPI_ROOT>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			fec1: ethernet@30be0000 {
				compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
				reg = <0x30be0000 0x10000>;