Commit 85761f45 authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo
Browse files

arm64: dts: imx8mq: Add ECSPI support 



Add support for the three ECSPI ports present on i.MX8MQ.

Signed-off-by: default avatarFabio Estevam <festevam@gmail.com>
Reviewed-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent f196ef19

arch/arm64/boot/dts/freescale/imx8mq.dtsi

+39 −0
Original line number Diff line number Diff line
@@ -25,6 +25,9 @@ 
		serial1 = &uart2;

		serial2 = &uart3;

		serial3 = &uart4;

		spi0 = &ecspi1;

		spi1 = &ecspi2;

		spi2 = &ecspi3;

	};



	ckil: clock-ckil {
@@ -383,6 +386,42 @@ 
			#size-cells = <1>;

			ranges = <0x30800000 0x30800000 0x400000>;



			ecspi1: spi@30820000 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";

				reg = <0x30820000 0x10000>;

				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,

					 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;

				clock-names = "ipg", "per";

				status = "disabled";

			};



			ecspi2: spi@30830000 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";

				reg = <0x30830000 0x10000>;

				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,

					 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;

				clock-names = "ipg", "per";

				status = "disabled";

			};



			ecspi3: spi@30840000 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";

				reg = <0x30840000 0x10000>;

				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,

					 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;

				clock-names = "ipg", "per";

				status = "disabled";

			};



			uart1: serial@30860000 {

				compatible = "fsl,imx8mq-uart",

				             "fsl,imx6q-uart";

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