Commit 387a4c2b authored May 23, 2019 by Tina Zhang Committed by Zhenyu Wang May 30, 2019

drm/i915/gvt: Initialize intel_gvt_gtt_entry in stack



Stack struct intel_gvt_gtt_entry value needs to be initialized before
being used, as the fields may contain garbage values.

W/o this patch, set_ggtt_entry prints:
-------------------------------------
274.046840: set_ggtt_entry: vgpu1:set ggtt entry 0x9bed8000ffffe900
274.046846: set_ggtt_entry: vgpu1:set ggtt entry 0xe55df001
274.046852: set_ggtt_entry: vgpu1:set ggtt entry 0x9bed8000ffffe900

0x9bed8000 is the stack grabage.

W/ this patch, set_ggtt_entry prints:
------------------------------------
274.046840: set_ggtt_entry: vgpu1:set ggtt entry 0xffffe900
274.046846: set_ggtt_entry: vgpu1:set ggtt entry 0xe55df001
274.046852: set_ggtt_entry: vgpu1:set ggtt entry 0xffffe900

v2:
- Initialize during declaration. (Zhenyu)

Fixes: 7598e870 ("drm/i915/gvt: Missed to cancel dma map for ggtt entries")
Cc: stable@vger.kernel.org # v4.20+
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

parent 591c39ff

drivers/gpu/drm/i915/gvt/gtt.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -2183,7 +2183,8 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
		struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
		unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
		unsigned long gma, gfn;
		struct intel_gvt_gtt_entry e, m;
		struct intel_gvt_gtt_entry e = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
		struct intel_gvt_gtt_entry m = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
		dma_addr_t dma_addr;
		int ret;
		struct intel_gvt_partial_pte partial_pte, pos, *n;
		@@ -2250,7 +2251,8 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,

		if (!partial_update && (ops->test_present(&e))) {
		gfn = ops->get_pfn(&e);
		m = e;
		m.val64 = e.val64;
		m.type = e.type;

		/* one PTE update may be issued in multiple writes and the
		* first write may not construct a valid gfn

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