Commit 375ca548 authored by David S. Miller's avatar David S. Miller
Browse files


Two easily resolvable overlapping change conflicts, one in
TCP and one in the eBPF verifier.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 58066ac9 40e196a9
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@@ -7,7 +7,7 @@ Intro
=====

The MSG_ZEROCOPY flag enables copy avoidance for socket send calls.
The feature is currently implemented for TCP sockets.
The feature is currently implemented for TCP and UDP sockets.


Opportunity and Caveats
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@@ -2,7 +2,7 @@
VERSION = 5
PATCHLEVEL = 0
SUBLEVEL = 0
EXTRAVERSION = -rc6
EXTRAVERSION = -rc7
NAME = Shy Crocodile

# *DOCUMENTATION*
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@@ -1400,6 +1400,7 @@ config NR_CPUS
config HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs"
	depends on SMP
	select GENERIC_IRQ_MIGRATION
	help
	  Say Y here to experiment with turning CPUs off and on.  CPUs
	  can be controlled through /sys/devices/system/cpu.
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@@ -644,6 +644,17 @@
	};
};

/* Configure pwm clock source for timers 8 & 9 */
&timer8 {
	assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
	assigned-clock-parents = <&sys_clkin_ck>;
};

&timer9 {
	assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
	assigned-clock-parents = <&sys_clkin_ck>;
};

/*
 * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
 * uart1 wakeirq.
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@@ -317,7 +317,8 @@

	palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
		pinctrl-single,pins = <
			OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1 */
			/* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
			OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
		>;
	};

@@ -385,7 +386,8 @@

	palmas: palmas@48 {
		compatible = "ti,palmas";
		interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
		/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x48>;
		interrupt-controller;
		#interrupt-cells = <2>;
@@ -651,7 +653,8 @@
		pinctrl-names = "default";
		pinctrl-0 = <&twl6040_pins>;

		interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
		/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>;

		/* audpwron gpio defined in the board specific dts */

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