Commit 37276e00 authored by Chao Hao's avatar Chao Hao Committed by Joerg Roedel
Browse files

iommu/mediatek: Add sub_comm id in translation fault 



The max larb number that a iommu HW support is 8(larb0~larb7 in the below
diagram).
If the larb's number is over 8, we use a sub_common for merging
several larbs into one larb. At this case, we will extend larb_id:
bit[11:9] means common-id;
bit[8:7] means subcommon-id;
>From these two variables, we could get the real larb number when
translation fault happen.
The diagram is as below:
		 EMI
		  |
		IOMMU
		  |
           -----------------
	   |               |
	common1   	common0
	   |		   |
	   -----------------
		  |
             smi common
		  |
  ------------------------------------
  |       |       |       |     |    |
 3'd0    3'd1    3'd2    3'd3  ...  3'd7   <-common_id(max is 8)
  |       |       |       |     |    |
Larb0   Larb1     |     Larb3  ... Larb7
		  |
	    smi sub common
		  |
     --------------------------
     |        |       |       |
    2'd0     2'd1    2'd2    2'd3   <-sub_common_id(max is 4)
     |        |       |       |
   Larb8    Larb9   Larb10  Larb11

In this patch we extend larb_remap[] to larb_remap[8][4] for this.
larb_remap[x][y]: x means common-id above, y means subcommon_id above.

We can also distinguish if the M4U HW has sub_common by HAS_SUB_COMM
macro.

Signed-off-by: default avatarChao Hao <chao.hao@mediatek.com>
Reviewed-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20200703044127.27438-7-chao.hao@mediatek.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent b053bc71

drivers/iommu/mtk_iommu.c

+14 −7
Original line number Diff line number Diff line
@@ -91,6 +91,8 @@ 
#define REG_MMU1_INVLD_PA			0x148

#define REG_MMU0_INT_ID				0x150

#define REG_MMU1_INT_ID				0x154

#define F_MMU_INT_ID_COMM_ID(a)			(((a) >> 9) & 0x7)

#define F_MMU_INT_ID_SUB_COMM_ID(a)		(((a) >> 7) & 0x3)

#define F_MMU_INT_ID_LARB_ID(a)			(((a) >> 7) & 0x7)

#define F_MMU_INT_ID_PORT_ID(a)			(((a) >> 2) & 0x1f)
@@ -109,6 +111,7 @@ 
#define HAS_VLD_PA_RNG			BIT(2)

#define RESET_AXI			BIT(3)

#define OUT_ORDER_WR_EN			BIT(4)

#define HAS_SUB_COMM			BIT(5)



#define MTK_IOMMU_HAS_FLAG(pdata, _x) \

		((((pdata)->flags) & (_x)) == (_x))
@@ -239,7 +242,7 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 
	struct mtk_iommu_data *data = dev_id;

	struct mtk_iommu_domain *dom = data->m4u_dom;

	u32 int_state, regval, fault_iova, fault_pa;

	unsigned int fault_larb, fault_port;

	unsigned int fault_larb, fault_port, sub_comm = 0;

	bool layer, write;



	/* Read error info from registers */
@@ -255,10 +258,14 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) 
	}

	layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;

	write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;

	fault_larb = F_MMU_INT_ID_LARB_ID(regval);

	fault_port = F_MMU_INT_ID_PORT_ID(regval);



	fault_larb = data->plat_data->larbid_remap[fault_larb];

	if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {

		fault_larb = F_MMU_INT_ID_COMM_ID(regval);

		sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);

	} else {

		fault_larb = F_MMU_INT_ID_LARB_ID(regval);

	}

	fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];



	if (report_iommu_fault(&dom->domain, data->dev, fault_iova,

			       write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
@@ -785,21 +792,21 @@ static const struct mtk_iommu_plat_data mt2712_data = { 
	.m4u_plat     = M4U_MT2712,

	.flags        = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,

	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,

	.larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},

	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},

};



static const struct mtk_iommu_plat_data mt8173_data = {

	.m4u_plat     = M4U_MT8173,

	.flags	      = HAS_4GB_MODE | HAS_BCLK | RESET_AXI,

	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,

	.larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */

	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */

};



static const struct mtk_iommu_plat_data mt8183_data = {

	.m4u_plat     = M4U_MT8183,

	.flags        = RESET_AXI,

	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,

	.larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},

	.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},

};



static const struct of_device_id mtk_iommu_of_ids[] = {

drivers/iommu/mtk_iommu.h

+4 −1
Original line number Diff line number Diff line
@@ -17,6 +17,9 @@ 
#include <linux/spinlock.h>

#include <soc/mediatek/smi.h>



#define MTK_LARB_COM_MAX	8

#define MTK_LARB_SUBCOM_MAX	4



struct mtk_iommu_suspend_reg {

	union {

		u32			standard_axi_mode;/* v1 */
@@ -41,7 +44,7 @@ struct mtk_iommu_plat_data { 
	enum mtk_iommu_plat m4u_plat;

	u32                 flags;

	u32                 inv_sel_reg;

	unsigned char       larbid_remap[MTK_LARB_NR_MAX];

	unsigned char       larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];

};



struct mtk_iommu_domain;

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