Commit 3697b339 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: add lock protection for swSMU APIs V2 



This is a quick and low risk fix. Those APIs which
are exposed to other IPs or to support sysfs/hwmon
interfaces or DAL will have lock protection. Meanwhile
no lock protection is enforced for swSMU internal used
APIs. Future optimization is needed.

V2: strip the lock protection for all swSMU internal APIs

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Acked-by: default avatarAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6aec5bb4

drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c

+4 −2
Original line number Diff line number Diff line
@@ -911,7 +911,8 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) 
	if (is_support_sw_smu(adev)) {

		ret = smu_get_dpm_freq_range(&adev->smu, SMU_GFXCLK,

					     low ? &clk_freq : NULL,

					     !low ? &clk_freq : NULL);

					     !low ? &clk_freq : NULL,

					     true);

		if (ret)

			return 0;

		return clk_freq * 100;
@@ -928,7 +929,8 @@ int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) 
	if (is_support_sw_smu(adev)) {

		ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK,

					     low ? &clk_freq : NULL,

					     !low ? &clk_freq : NULL);

					     !low ? &clk_freq : NULL,

					     true);

		if (ret)

			return 0;

		return clk_freq * 100;

drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h

+0 −6
Original line number Diff line number Diff line
@@ -298,12 +298,6 @@ enum amdgpu_pcie_gen { 
#define amdgpu_dpm_get_current_power_state(adev) \

		((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))



#define amdgpu_smu_get_current_power_state(adev) \

		((adev)->smu.ppt_funcs->get_current_power_state(&((adev)->smu)))



#define amdgpu_smu_set_power_state(adev) \

		((adev)->smu.ppt_funcs->set_power_state(&((adev)->smu)))



#define amdgpu_dpm_get_pp_num_states(adev, data) \

		((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+12 −11
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev, 


	if (is_support_sw_smu(adev)) {

		if (adev->smu.ppt_funcs->get_current_power_state)

			pm = amdgpu_smu_get_current_power_state(adev);

			pm = smu_get_current_power_state(&adev->smu);

		else

			pm = adev->pm.dpm.user_state;

	} else if (adev->powerplay.pp_funcs->get_current_power_state) {
@@ -907,7 +907,7 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 
		return ret;



	if (is_support_sw_smu(adev))

		ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);

		ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);

	else if (adev->powerplay.pp_funcs->force_clock_level)

		ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
@@ -954,7 +954,7 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 
		return ret;



	if (is_support_sw_smu(adev))

		ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);

		ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);

	else if (adev->powerplay.pp_funcs->force_clock_level)

		ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
@@ -994,7 +994,7 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, 
		return ret;



	if (is_support_sw_smu(adev))

		ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);

		ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);

	else if (adev->powerplay.pp_funcs->force_clock_level)

		ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
@@ -1034,7 +1034,7 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, 
		return ret;



	if (is_support_sw_smu(adev))

		ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);

		ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);

	else if (adev->powerplay.pp_funcs->force_clock_level)

		ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
@@ -1074,7 +1074,7 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, 
		return ret;



	if (is_support_sw_smu(adev))

		ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);

		ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);

	else if (adev->powerplay.pp_funcs->force_clock_level)

		ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
@@ -1114,7 +1114,7 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 
		return ret;



	if (is_support_sw_smu(adev))

		ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);

		ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);

	else if (adev->powerplay.pp_funcs->force_clock_level)

		ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
@@ -1306,7 +1306,7 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, 
	}

	parameter[parameter_size] = profile_mode;

	if (is_support_sw_smu(adev))

		ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);

		ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);

	else if (adev->powerplay.pp_funcs->set_power_profile_mode)

		ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);

	if (!ret)
@@ -2015,7 +2015,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, 
	uint32_t limit = 0;



	if (is_support_sw_smu(adev)) {

		smu_get_power_limit(&adev->smu, &limit, true);

		smu_get_power_limit(&adev->smu, &limit, true, true);

		return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);

	} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {

		adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
@@ -2033,7 +2033,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, 
	uint32_t limit = 0;



	if (is_support_sw_smu(adev)) {

		smu_get_power_limit(&adev->smu, &limit, false);

		smu_get_power_limit(&adev->smu, &limit, false,  true);

		return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);

	} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {

		adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
@@ -3013,7 +3013,8 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) 
		struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;

		smu_handle_task(&adev->smu,

				smu_dpm->dpm_level,

				AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);

				AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,

				true);

	} else {

		if (adev->powerplay.pp_funcs->dispatch_tasks) {

			if (!amdgpu_device_has_dc_support(adev)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

+3 −3
Original line number Diff line number Diff line
@@ -865,7 +865,7 @@ enum pp_smu_status pp_nv_get_maximum_sustainable_clocks( 
	if (!smu->funcs->get_max_sustainable_clocks_by_dc)

		return PP_SMU_RESULT_UNSUPPORTED;



	if (!smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks))

	if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))

		return PP_SMU_RESULT_OK;



	return PP_SMU_RESULT_FAIL;
@@ -884,7 +884,7 @@ enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp, 
	if (!smu->ppt_funcs->get_uclk_dpm_states)

		return PP_SMU_RESULT_UNSUPPORTED;



	if (!smu->ppt_funcs->get_uclk_dpm_states(smu,

	if (!smu_get_uclk_dpm_states(smu,

			clock_values_in_khz, num_states))

		return PP_SMU_RESULT_OK;
@@ -905,7 +905,7 @@ enum pp_smu_status pp_rn_get_dpm_clock_table( 
	if (!smu->ppt_funcs->get_dpm_clock_table)

		return PP_SMU_RESULT_UNSUPPORTED;



	if (!smu->ppt_funcs->get_dpm_clock_table(smu, clock_table))

	if (!smu_get_dpm_clock_table(smu, clock_table))

		return PP_SMU_RESULT_OK;



	return PP_SMU_RESULT_FAIL;

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+650 −50

File changed.

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