Commit 6aec5bb4 authored by Jane Jian's avatar Jane Jian Committed by Alex Deucher
Browse files

drm/amdgpu: add VCN0 and VCN1 needed headers 



Add mmsch part registers

Signed-off-by: default avatarJane Jian <jane.jian@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6fcca317

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h

+12 −0
Original line number Diff line number Diff line
@@ -24,6 +24,18 @@ 


// addressBlock: uvd0_mmsch_dec

// base address: 0x1e000

#define mmMMSCH_VF_VMID                                                                                0x000b

#define mmMMSCH_VF_VMID_BASE_IDX                                                                       0

#define mmMMSCH_VF_CTX_ADDR_LO                                                                         0x000c

#define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX                                                                0

#define mmMMSCH_VF_CTX_ADDR_HI                                                                         0x000d

#define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX                                                                0

#define mmMMSCH_VF_CTX_SIZE                                                                            0x000e

#define mmMMSCH_VF_CTX_SIZE_BASE_IDX                                                                   0

#define mmMMSCH_VF_MAILBOX_HOST                                                                        0x0012

#define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX                                                               0

#define mmMMSCH_VF_MAILBOX_RESP                                                                        0x0013

#define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX                                                               0





// addressBlock: uvd0_jpegnpdec

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