Commit 356fdfbe authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Catalin Marinas
Browse files

arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register 



Enable EVT, BBM, TTL, IDS, ST, NV and CCIDX features bits in ID_AA64MMFR2
register as per ARM DDI 0487F.a specification.

Suggested-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Link: https://lore.kernel.org/r/1593748297-1965-4-git-send-email-anshuman.khandual@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 853772ba

arch/arm64/include/asm/sysreg.h

+7 −0
Original line number Diff line number Diff line
@@ -753,8 +753,15 @@ 


/* id_aa64mmfr2 */

#define ID_AA64MMFR2_E0PD_SHIFT		60

#define ID_AA64MMFR2_EVT_SHIFT		56

#define ID_AA64MMFR2_BBM_SHIFT		52

#define ID_AA64MMFR2_TTL_SHIFT		48

#define ID_AA64MMFR2_FWB_SHIFT		40

#define ID_AA64MMFR2_IDS_SHIFT		36

#define ID_AA64MMFR2_AT_SHIFT		32

#define ID_AA64MMFR2_ST_SHIFT		28

#define ID_AA64MMFR2_NV_SHIFT		24

#define ID_AA64MMFR2_CCIDX_SHIFT	20

#define ID_AA64MMFR2_LVA_SHIFT		16

#define ID_AA64MMFR2_IESB_SHIFT		12

#define ID_AA64MMFR2_LSM_SHIFT		8

arch/arm64/kernel/cpufeature.c

+7 −0
Original line number Diff line number Diff line
@@ -330,8 +330,15 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 


static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),

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